43 lines
2.4 KiB
C
43 lines
2.4 KiB
C
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// I have reduced noops at the end of each of these to take into account that there are several additional clock ticks of setup, after. However, I'm not totally sure that I get things right, seeing that there are four possible sequences, and I'm not really accounting for the timing of all four of them.
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#define write_zero(port, bit) \
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__asm__ __volatile__ ( \
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"sbi %0, %1" "\n\t" \
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"nop" "\n\t" \
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"cbi %0, %1" "\n\t" \
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"nop" "\n\t" \
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: /* no outputs */ \
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: "I" (_SFR_IO_ADDR(port)), \
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"I" (bit) \
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)
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#define write_one(port, bit) \
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__asm__ __volatile__ ( \
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"sbi %0, %1" "\n\t" \
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"nop" "\n\t" \
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"nop" "\n\t" \
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"nop" "\n\t" \
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"nop" "\n\t" \
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"nop" "\n\t" \
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"cbi %0, %1" "\n\t" \
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: /* no outputs */ \
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: "I" (_SFR_IO_ADDR(port)), \
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"I" (bit) \
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)
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#define write_byte(port, bit, byte) \
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__asm__ __volatile__ ( \
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"ldi %z, 8" "\n\t" \ // count out eight bits
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"ld __tmp_reg__, %[byte]" "\n\t" \ // load the current byte into a temporary register
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"L_%=: " "lsl __tmp_reg__" "\n\t" \ // shift the temporary register left, saving the msb in SREG (1 cycle)
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"brbs I_%=" "\n\t" \ // if SREG is set, branch to I_%= (2 cycles if true, 1 cycle if false)
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write_zero(port, bit) \ // SREG was zero, so write a zero to the port
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"rjmp J_%=" "\n\t" \ // Jump to J_%=, the loop cleanup (2 cycles)
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"I_%=: " write_one(port, bit) \ // SREG was one, so write a one to the port
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"J_%=: " "dec %z" "\n\t" \ // Decrement the bits counter (1 cycle)
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"cpi %z, 0" "\n\t" \ // are there any bits left to send? (1 cycle)
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"brne L_%=" "\n\t" \ // there are, so go back to L_%= (2 cycles)
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: /* no outputs */ \
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: [byte] "I" (byte) \
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)
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