Attempting to communicate with the TFT
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parent
506a13e802
commit
93b84ee72d
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[build]
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target = "thumbv6m-none-eabi"
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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
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runner = "elf2uf2-rs -d -s"
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[package]
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name = "e-ink"
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version = "0.1.0"
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edition = "2021"
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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[dependencies]
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embassy-embedded-hal = { version = "0.1.0", features = ["defmt"] }
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embassy-sync = { version = "0.6.0", features = ["defmt"] }
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embassy-executor = { version = "0.5.0", features = ["task-arena-size-98304", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
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embassy-time = { version = "0.3.1", features = ["defmt", "defmt-timestamp-uptime"] }
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embassy-rp = { version = "0.1.0", features = ["defmt", "unstable-pac", "time-driver", "critical-section-impl"] }
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defmt = "0.3"
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defmt-rtt = "0.4"
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cortex-m-rt = "0.7.0"
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panic-probe = { version = "0.3", features = ["print-defmt"] }
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embedded-hal = "1.0.0"
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use std::env;
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use std::fs::File;
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use std::io::Write;
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use std::path::PathBuf;
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fn main() {
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// Put `memory.x` in our output directory and ensure it's
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// on the linker search path.
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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File::create(out.join("memory.x"))
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.unwrap()
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.write_all(include_bytes!("memory.x"))
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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// By default, Cargo will re-run a build script whenever
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// any file in the project changes. By specifying `memory.x`
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// here, we ensure the build script is only re-run when
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// `memory.x` is changed.
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println!("cargo:rerun-if-changed=memory.x");
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println!("cargo:rustc-link-arg-bins=--nmagic");
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println!("cargo:rustc-link-arg-bins=-Tlink.x");
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println!("cargo:rustc-link-arg-bins=-Tlink-rp.x");
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println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
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}
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MEMORY {
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BOOT2 : ORIGIN = 0x10000000, LENGTH = 0x100
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FLASH : ORIGIN = 0x10000100, LENGTH = 2048K - 0x100
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/*
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* RAM consists of 4 banks, SRAM0-SRAM3, with a striped mapping.
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* This is usually good for performance, as it distributes load on
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* those banks evenly.
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*/
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RAM : ORIGIN = 0x20000000, LENGTH = 256K
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/*
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* RAM banks 4 and 5 use a direct mapping. They can be used to have
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* memory areas dedicated for some specific job, improving predictability
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* of access times.
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* Example: Separate stacks for core0 and core1.
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*/
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SRAM4 : ORIGIN = 0x20040000, LENGTH = 4k
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SRAM5 : ORIGIN = 0x20041000, LENGTH = 4k
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/* SRAM banks 0-3 can also be accessed directly. However, those ranges
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alias with the RAM mapping, above. So don't use them at the same time!
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SRAM0 : ORIGIN = 0x21000000, LENGTH = 64k
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SRAM1 : ORIGIN = 0x21010000, LENGTH = 64k
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SRAM2 : ORIGIN = 0x21020000, LENGTH = 64k
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SRAM3 : ORIGIN = 0x21030000, LENGTH = 64k
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*/
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}
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EXTERN(BOOT2_FIRMWARE)
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SECTIONS {
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/* ### Boot loader */
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.boot2 ORIGIN(BOOT2) :
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{
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KEEP(*(.boot2));
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} > BOOT2
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} INSERT BEFORE .text;
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#![no_std]
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#![no_main]
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use embassy_executor::Spawner;
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use embassy_rp::{spi, spi::Spi, gpio};
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use embedded_hal::delay::DelayNs;
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use embassy_time::Delay;
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use gpio::{Level, Output};
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use defmt::*;
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use defmt_rtt as _;
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use panic_probe as _;
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/*
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* width: 320
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* height: 170
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*/
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fn software_reset<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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dcx.set_low();
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let _ = spi.blocking_write(&[0x01]);
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timer.delay_ms(150);
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}
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fn sleep_out<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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dcx.set_low();
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let _ = spi.blocking_write(&[0x11]);
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timer.delay_ms(10);
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}
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fn color_mode<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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dcx.set_low();
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let _ = spi.blocking_write(&[0x11]);
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dcx.set_high();
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let _ = spi.blocking_write(&[0x63]);
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timer.delay_ms(10);
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}
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fn normal_display<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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dcx.set_low();
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let _ = spi.blocking_write(&[0x13]);
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timer.delay_ms(10);
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}
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fn display_on<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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dcx.set_low();
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let _ = spi.blocking_write(&[0x29]);
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timer.delay_ms(10);
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}
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fn memory_address_set<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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dcx.set_low();
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spi.blocking_write(&[0x36]);
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dcx.set_high();
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spi.blocking_write(&[0x08]);
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timer.delay_ms(10);
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}
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fn column_set<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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let width: u16 = 320;
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dcx.set_low();
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let _ = spi.blocking_write(&[0x2a]);
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dcx.set_high();
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let _ = spi.blocking_write(&[0x0, 0x0, (width >> 8) as u8, (width & 0xff) as u8]);
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timer.delay_ms(10);
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}
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fn row_set<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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let height: u16 = 170;
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dcx.set_low();
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let _ = spi.blocking_write(&[0x2b]);
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dcx.set_high();
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let _ = spi.blocking_write(&[0x0, 0x0, (height >> 8) as u8, (170 & 0xff) as u8]);
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timer.delay_ms(10);
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}
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fn write_image<T, M, R>(spi: &mut Spi<T, M>, timer: &mut Delay, dcx: &mut Output<R>)
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where
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T: embassy_rp::spi::Instance,
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M: embassy_rp::spi::Mode,
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R: embassy_rp::gpio::Pin,
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{
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dcx.set_low();
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let _ = spi.blocking_write(&[0x2c]);
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dcx.set_high();
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let mut buf: [u8; 320 * 170 * 3] = [0; 320 * 170 * 3];
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buf[0] = 0xff;
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buf[2] = 0xff;
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buf[3] = 0xff;
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let _ = spi.blocking_write(&buf);
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}
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p = embassy_rp::init(Default::default());
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let mut timer = Delay;
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let mut tft_select = Output::new(p.PIN_10, Level::High); /* Pull low to activate the chip */
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let mut tft_reset = Output::new(p.PIN_11, Level::Low);
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timer.delay_ms(10);
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tft_reset.set_high();
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let mut dcx = Output::new(p.PIN_15, Level::Low); /* Low == Command, High == Data */
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let mut spi_config = spi::Config::default();
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spi_config.frequency = 2_000_000;
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let mut spi = embassy_rp::spi::Spi::new_blocking(
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p.SPI0,
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p.PIN_2,
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p.PIN_3,
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p.PIN_4,
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spi_config
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);
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tft_select.set_low();
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/* Software reset, 150ms delay */
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software_reset(&mut spi, &mut timer, &mut dcx);
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/* 10 ms delay after each additonal command */
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/* Sleep out */
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sleep_out(&mut spi, &mut timer, &mut dcx);
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/* Color mode */
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color_mode(&mut spi, &mut timer, &mut dcx);
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/* Memory access ctrl */
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memory_address_set(&mut spi, &mut timer, &mut dcx);
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/* Column addr set */
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column_set(&mut spi, &mut timer, &mut dcx);
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/* Row addr set */
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row_set(&mut spi, &mut timer, &mut dcx);
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/* Normal Display on */
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normal_display(&mut spi, &mut timer, &mut dcx);
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/* Main screen on */
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display_on(&mut spi, &mut timer, &mut dcx);
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write_image(&mut spi, &mut timer, &mut dcx);
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tft_select.set_high();
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}
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