diff --git a/build.rs b/build.rs index bff50ac..6a16bcc 100644 --- a/build.rs +++ b/build.rs @@ -71,7 +71,7 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> { fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { writeln!(w, "//! Core for {}.", mcu.device.name)?; writeln!(w)?; - writeln!(w, "use {{Mask, Bitset, HardwareUsart, Register}};")?; + writeln!(w, "use {{Mask, Bitset, Register}};")?; writeln!(w, "use modules;")?; writeln!(w)?; @@ -221,7 +221,7 @@ mod gen { writeln!(w, "/// The {} module.", usart.name)?; writeln!(w, "pub struct {};", usart.name)?; writeln!(w)?; - writeln!(w, "impl HardwareUsart for {} {{", usart.name)?; + writeln!(w, "impl modules::HardwareUsart for {} {{", usart.name)?; for register in usart.registers.iter() { let reg_ty = if register.name.starts_with("UDR") { // the data register. "DataRegister".to_owned() @@ -276,6 +276,41 @@ mod gen { writeln!(w, "}}")?; } + if let Some(tc) = mcu.module("TC16") { // Timer/Counter, 16-bit. + const TYPE_NAME: &'static str = "Timer16"; + + let find_reg = |name: &'static str| { + tc.registers().find(|r| r.name.starts_with(name)) + .expect(&format!("could not find '{}' register", name)) + }; + let find_reg_suffix = |name: &'static str, suffix: &'static str| { + tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix)) + .expect(&format!("could not find '{}' register", name)) + }; + + writeln!(w, "/// 16-bit timer.")?; + writeln!(w, "pub struct {};", TYPE_NAME)?; + writeln!(w)?; + writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?; + writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?; + writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?; + writeln!(w, " type Counter = {};", find_reg("TCNT").name)?; + writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?; + writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?; + writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?; + writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?; + writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?; + writeln!(w, " const CS0: Mask = Self::ControlB::CS10;")?; + writeln!(w, " const CS1: Mask = Self::ControlB::CS11;")?; + writeln!(w, " const CS2: Mask = Self::ControlB::CS12;")?; + writeln!(w, " const WGM0: Mask = Self::ControlA::WGM10;")?; + writeln!(w, " const WGM1: Mask = Self::ControlA::WGM11;")?; + writeln!(w, " const WGM2: Mask = Self::ControlB::WGM10;")?; + writeln!(w, " const WGM3: Mask = Self::ControlB::WGM11;")?; + writeln!(w, " const OCIEA: Bitset = Self::InterruptMask::OCIE1A;")?; + writeln!(w, "}}")?; + } + Ok(()) } diff --git a/src/lib.rs b/src/lib.rs index 6b37278..88501b1 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -15,7 +15,6 @@ pub use self::register::{Bitset, Mask, Register, RegisterValue}; pub use self::pin::Pin; -pub use self::usart::HardwareUsart; pub mod prelude; pub mod serial; @@ -26,7 +25,6 @@ pub mod config; mod register; mod pin; -mod usart; #[doc(hidden)] pub mod std_stub; diff --git a/src/modules/mod.rs b/src/modules/mod.rs index f8ac3bd..371c7ac 100644 --- a/src/modules/mod.rs +++ b/src/modules/mod.rs @@ -2,7 +2,9 @@ pub use self::spi::HardwareSpi; pub use self::timer::{Timer8, Timer8Setup, Timer16, Timer16Setup}; +pub use self::usart::HardwareUsart; mod spi; mod timer; +mod usart; diff --git a/src/modules/timer/timer16.rs b/src/modules/timer/timer16.rs index 2f4d7c9..24456d8 100644 --- a/src/modules/timer/timer16.rs +++ b/src/modules/timer/timer16.rs @@ -48,9 +48,11 @@ pub trait Timer16 { const WGM0: Mask; const WGM1: Mask; const WGM2: Mask; - const WGM3: Mask; // fixme: right reg? + const WGM3: Mask; const OCIEA: Bitset; + + fn setup() -> Timer16Setup { Timer16Setup::new() } } pub enum ClockSource { @@ -152,7 +154,7 @@ pub struct Timer16Setup { impl Timer16Setup { #[inline] - pub fn new() -> Self { + fn new() -> Self { Timer16Setup { a: Mask::zero(), b: Mask::zero(), @@ -190,22 +192,19 @@ impl Timer16Setup { #[inline] pub fn configure(self) { - unsafe { - T::ControlA::write(self.a); - T::ControlB::write(self.b); - T::ControlC::write(self.c); + T::ControlA::write(self.a); + T::ControlB::write(self.b); + T::ControlC::write(self.c); - // Reset counter to zero - T::Counter::write(0u16); + // Reset counter to zero + T::Counter::write(0u16); - if let Some(v) = self.output_compare_1 { - // Set the match - T::CompareA::write(v); + if let Some(v) = self.output_compare_1 { + // Set the match + T::CompareA::write(v); - // Enable compare interrupt - // FIXME: uncomment - // write_volatile(TIMSK1, OCIE1A); - } + // Enable compare interrupt + T::OCIEA.set_all(); } } } diff --git a/src/modules/timer/timer8.rs b/src/modules/timer/timer8.rs index cdc55d1..4da6603 100644 --- a/src/modules/timer/timer8.rs +++ b/src/modules/timer/timer8.rs @@ -165,21 +165,18 @@ impl Timer8Setup { #[inline] pub fn configure(self) { - unsafe { - T::ControlA::write(self.a); - T::ControlB::write(self.b); + T::ControlA::write(self.a); + T::ControlB::write(self.b); - // Reset counter to zero - T::Counter::write(0); + // Reset counter to zero + T::Counter::write(0); - if let Some(v) = self.output_compare_1 { - // Set the match - T::CompareA::write(v); + if let Some(v) = self.output_compare_1 { + // Set the match + T::CompareA::write(v); - // Enable compare interrupt - // FIXME: is this right? - T::OCIEA.set_all(); - } + // Enable compare interrupt + T::OCIEA.set_all(); } } } diff --git a/src/usart.rs b/src/modules/usart.rs similarity index 100% rename from src/usart.rs rename to src/modules/usart.rs