From 1f638dbea3cc9206786e12a394da68c2381d6d6d Mon Sep 17 00:00:00 2001
From: Dylan McKay <me@dylanmckay.io>
Date: Wed, 13 Dec 2017 22:24:16 +1300
Subject: [PATCH] Add a timer trait

---
 src/lib.rs   |  2 ++
 src/timer.rs | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 src/timer.rs

diff --git a/src/lib.rs b/src/lib.rs
index 4970f7d..6000613 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -15,6 +15,7 @@
 
 pub use self::register::{Bitset, Mask, Register, RegisterValue};
 pub use self::pin::Pin;
+pub use self::timer::Timer8;
 pub use self::usart::HardwareUsart;
 
 pub mod prelude;
@@ -29,6 +30,7 @@ pub mod config;
 mod register;
 mod pin;
 mod usart;
+mod timer;
 #[doc(hidden)]
 pub mod std_stub;
 
diff --git a/src/timer.rs b/src/timer.rs
new file mode 100644
index 0000000..4793dde
--- /dev/null
+++ b/src/timer.rs
@@ -0,0 +1,38 @@
+use {Register};
+
+/// An 8-bit timer.
+pub trait Timer8 {
+    /// The first compare register.
+    /// For example, OCR0A.
+    type CompareA: Register<u8>;
+
+    /// The second compare register.
+    /// For example, OCR0B.
+    type CompareB: Register<u8>;
+
+    /// The counter register.
+    ///
+    /// For example, TCNT0.
+    type Counter: Register<u8>;
+
+    /// The first control register.
+    ///
+    /// For example, TCCR0A.
+    type ControlA: Register<u8>;
+
+    /// The second control register.
+    ///
+    /// For example, TCCR0B.
+    type ControlB: Register<u8>;
+
+    /// The interrupt mask register.
+    ///
+    /// For example, TIMSK0.
+    type InterruptMask: Register<u8>;
+
+    /// The interrupt flag register.
+    ///
+    /// For example, TIFR0.
+    type InterruptFlag: Register<u8>;
+}
+