diff --git a/build.rs b/build.rs
index 1ccf925..993c088 100644
--- a/build.rs
+++ b/build.rs
@@ -53,12 +53,13 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
 fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
     writeln!(w, "//! Core for {}.", mcu.device.name)?;
     writeln!(w)?;
-    writeln!(w, "use {{HardwareSpi, Pin, Register}};")?;
+    writeln!(w, "use {{HardwareSpi, HardwareUsart, Pin, Register}};")?;
     writeln!(w)?;
 
     gen::write_registers(mcu, w)?;
     gen::write_pins(mcu, w)?;
     gen::write_spi_modules(mcu, w)?;
+    gen::write_usarts(mcu, w)?;
 
     writeln!(w)
 }
@@ -152,6 +153,32 @@ mod gen {
         Ok(())
     }
 
+    pub fn write_usarts(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
+        if let Some(module) = mcu.module("USART") {
+            for usart in module.register_groups.iter() {
+                writeln!(w, "pub struct {};", usart.name)?;
+                writeln!(w)?;
+                writeln!(w, "impl HardwareUsart for {} {{", usart.name)?;
+                for register in usart.registers.iter() {
+                    let reg_ty = if register.name.starts_with("UDR") { // the data register.
+                        "UDR".to_owned()
+                    } else if register.name.starts_with("UCSR") { // one of the three control/status registers.
+                        let suffix = register.name.chars().rev().next().unwrap();
+                        format!("UCSR{}", suffix)
+                    } else if register.name.starts_with("UBRR") { // the baud rate register.
+                        "UBRR".to_owned()
+                    } else {
+                        panic!("unknown usart register '{}'", register.name);
+                    };
+                    writeln!(w, "    type {} = {};", reg_ty, register.name)?;
+                }
+                writeln!(w, "}}")?;
+                writeln!(w)?;
+            }
+        }
+        Ok(())
+    }
+
     /// Gets the name of a pin.
     fn pin_name(instance: &Instance, signal: &Signal) -> String {
         let idx = signal.index.expect("signal with no index");
diff --git a/src/lib.rs b/src/lib.rs
index 599ac9f..4fc6780 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -11,6 +11,7 @@
 pub use self::reg::Register;
 pub use self::pin::Pin;
 pub use self::spi::HardwareSpi;
+pub use self::usart::HardwareUsart;
 
 pub mod prelude;
 pub mod serial;
@@ -21,6 +22,7 @@ pub mod cores;
 mod reg;
 mod pin;
 mod spi;
+mod usart;
 
 pub enum DataDirection {
     Input,
diff --git a/src/usart.rs b/src/usart.rs
new file mode 100644
index 0000000..c378138
--- /dev/null
+++ b/src/usart.rs
@@ -0,0 +1,14 @@
+use Register;
+
+pub trait HardwareUsart {
+    /// The USART data register.
+    type UDR: Register<u8>;
+    /// USART control and status register A.
+    type UCSRA: Register<u8>;
+    /// USART control and status register B.
+    type UCSRB: Register<u8>;
+    /// USART control and status register C.
+    type UCSRC: Register<u8>;
+    /// USART baud rate register.
+    type UBRR: Register<u16>;
+}