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Improve the names of the Spi trait consts

This commit is contained in:
Dylan McKay 2017-08-31 02:05:59 +12:00
parent 394e07e160
commit 61b32145df
2 changed files with 49 additions and 44 deletions
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19
build.rs
View File

@ -133,15 +133,23 @@ mod gen {
.expect("no port signal associated with the spi signal pad"); .expect("no port signal associated with the spi signal pad");
let pin_name = self::pin_name(port_instance, port_signal); let pin_name = self::pin_name(port_instance, port_signal);
writeln!(w, " type {} = {};", spi_signal_name, pin_name)?; let const_name = match &spi_signal_name[..] {
"MISO" => "MasterInSlaveOut",
"MOSI" => "MasterOutSlaveIn",
"SCK" => "Clock",
"SS" => "SlaveSelect",
_ => panic!("unknown spi signal name: '{}'", spi_signal_name),
};
writeln!(w, " type {} = {};", const_name, pin_name)?;
} }
for reg in module.registers() { for reg in module.registers() {
let const_name = match &reg.caption[..] { let const_name = match &reg.caption[..] {
"SPI Data Register" => "SPDR", "SPI Data Register" => "DataRegister",
"SPI Status Register" => "SPSR", "SPI Status Register" => "StatusRegister",
"SPI Control Register" => "SPCR", "SPI Control Register" => "ControlRegister",
_ => panic!("unknown SPI module register: '{}'", reg.caption), _ => panic!("unknown SPI module register: {}", reg.caption),
}; };
@ -156,6 +164,7 @@ mod gen {
pub fn write_usarts(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { pub fn write_usarts(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
if let Some(module) = mcu.module("USART") { if let Some(module) = mcu.module("USART") {
for usart in module.register_groups.iter() { for usart in module.register_groups.iter() {
writeln!(w, "/// The {} module.", usart.name)?;
writeln!(w, "pub struct {};", usart.name)?; writeln!(w, "pub struct {};", usart.name)?;
writeln!(w)?; writeln!(w)?;
writeln!(w, "impl HardwareUsart for {} {{", usart.name)?; writeln!(w, "impl HardwareUsart for {} {{", usart.name)?;

74
src/spi.rs
View File

@ -6,29 +6,25 @@ use {Register, Pin};
/// Information at /// Information at
/// http://maxembedded.com/2013/11/the-spi-of-the-avr/ /// http://maxembedded.com/2013/11/the-spi-of-the-avr/
pub trait HardwareSpi { pub trait HardwareSpi {
/// Master-in slave-out pin. type MasterInSlaveOut: Pin;
type MISO: Pin; type MasterOutSlaveIn: Pin;
/// Master-out slave-in pin. type Clock: Pin;
type MOSI: Pin; type SlaveSelect: Pin;
/// Serial clock pin.
type SCK: Pin;
/// Slave-select pin.
type SS: Pin;
/// The SPI control register. /// The SPI control register.
type SPCR: Register<u8>; type ControlRegister: Register<u8>;
/// The SPI status register. /// The SPI status register.
type SPSR: Register<u8>; type StatusRegister: Register<u8>;
/// The SPI data register. /// The SPI data register.
type SPDR: Register<u8>; type DataRegister: Register<u8>;
/// Sets up the SPI as a master. /// Sets up the SPI as a master.
fn setup_master() { fn setup_master() {
// Setup DDR registers. // Setup DDR registers.
Self::MISO::set_input(); Self::MasterInSlaveOut::set_input();
Self::MOSI::set_output(); Self::MasterOutSlaveIn::set_output();
Self::SCK::set_output(); Self::Clock::set_output();
Self::SS::set_input(); Self::SlaveSelect::set_input();
Self::set_master(); Self::set_master();
Self::enable_interrupt(); Self::enable_interrupt();
@ -38,10 +34,10 @@ pub trait HardwareSpi {
/// Sets up the SPI as a slave. /// Sets up the SPI as a slave.
fn setup_slave() { fn setup_slave() {
// Setup DDR registers. // Setup DDR registers.
Self::MISO::set_output(); Self::MasterInSlaveOut::set_output();
Self::MOSI::set_input(); Self::MasterOutSlaveIn::set_input();
Self::SCK::set_input(); Self::Clock::set_input();
Self::SS::set_input(); Self::SlaveSelect::set_input();
Self::set_slave(); Self::set_slave();
Self::enable(); Self::enable();
@ -50,95 +46,95 @@ pub trait HardwareSpi {
/// Enables interrupts for the spi module. /// Enables interrupts for the spi module.
#[inline(always)] #[inline(always)]
fn enable_interrupt() { fn enable_interrupt() {
Self::SPCR::set(spcr::INTERRUPT_ENABLE); Self::ControlRegister::set(control_register::INTERRUPT_ENABLE);
} }
/// Disables interrupts for the spi module. /// Disables interrupts for the spi module.
#[inline(always)] #[inline(always)]
fn disable_interrupt() { fn disable_interrupt() {
Self::SPCR::unset(spcr::INTERRUPT_ENABLE); Self::ControlRegister::unset(control_register::INTERRUPT_ENABLE);
} }
/// Enables the SPI. /// Enables the SPI.
#[inline(always)] #[inline(always)]
fn enable() { fn enable() {
Self::SPCR::set(spcr::ENABLE); Self::ControlRegister::set(control_register::ENABLE);
} }
/// Disables the SPI. /// Disables the SPI.
#[inline(always)] #[inline(always)]
fn disable() { fn disable() {
Self::SPCR::unset(spcr::ENABLE); Self::ControlRegister::unset(control_register::ENABLE);
} }
/// Enables least-significant-bit first. /// Enables least-significant-bit first.
#[inline(always)] #[inline(always)]
fn set_lsb() { fn set_lsb() {
Self::SPCR::set(spcr::DATA_ORDER_LSB); Self::ControlRegister::set(control_register::DATA_ORDER_LSB);
} }
/// Enables most-significant-bit first. /// Enables most-significant-bit first.
#[inline(always)] #[inline(always)]
fn set_msb() { fn set_msb() {
Self::SPCR::unset(spcr::DATA_ORDER_LSB); Self::ControlRegister::unset(control_register::DATA_ORDER_LSB);
} }
/// Enables master mode. /// Enables master mode.
#[inline(always)] #[inline(always)]
fn set_master() { fn set_master() {
Self::SPCR::set(spcr::MASTER); Self::ControlRegister::set(control_register::MASTER);
} }
/// Enables slave mode. /// Enables slave mode.
#[inline(always)] #[inline(always)]
fn set_slave() { fn set_slave() {
Self::SPCR::unset(spcr::MASTER); Self::ControlRegister::unset(control_register::MASTER);
} }
/// Enables double speed mode. /// Enables double speed mode.
#[inline(always)] #[inline(always)]
fn enable_double_speed() { fn enable_double_speed() {
Self::SPSR::set(spsr::SPI2X); Self::StatusRegister::set(status_register::SPI2X);
} }
/// Disables double speed mode. /// Disables double speed mode.
#[inline(always)] #[inline(always)]
fn disable_double_speed() { fn disable_double_speed() {
Self::SPSR::unset(spsr::SPI2X); Self::StatusRegister::unset(status_register::SPI2X);
} }
/// Checks if there is a write collision. /// Checks if there is a write collision.
#[inline(always)] #[inline(always)]
fn is_write_collision() -> bool { fn is_write_collision() -> bool {
Self::SPSR::is_set(spsr::WCOL) Self::StatusRegister::is_set(status_register::WCOL)
} }
/// Sends a byte through the serial. /// Sends a byte through the serial.
#[inline(always)] #[inline(always)]
fn send_byte(byte: u8) { fn send_byte(byte: u8) {
Self::SPDR::write(byte); Self::DataRegister::write(byte);
Self::SPSR::wait_until_set(spsr::SPIF); Self::StatusRegister::wait_until_set(status_register::SPIF);
} }
/// Reads a byte from the serial. /// Reads a byte from the serial.
#[inline(always)] #[inline(always)]
fn receive_byte() -> u8 { fn receive_byte() -> u8 {
Self::SPSR::wait_until_set(spsr::SPIF); Self::StatusRegister::wait_until_set(status_register::SPIF);
Self::SPDR::read() Self::DataRegister::read()
} }
/// Sends and receives a byte. /// Sends and receives a byte.
#[inline(always)] #[inline(always)]
fn send_receive(byte: u8) -> u8 { fn send_receive(byte: u8) -> u8 {
Self::SPDR::write(byte); Self::DataRegister::write(byte);
Self::SPSR::wait_until_set(spsr::SPIF); Self::StatusRegister::wait_until_set(status_register::SPIF);
Self::SPDR::read() Self::DataRegister::read()
} }
} }
/// Constants for the control register. /// Constants for the control register.
#[allow(dead_code)] #[allow(dead_code)]
mod spcr { mod control_register {
pub const INTERRUPT_ENABLE: u8 = 1<<7; pub const INTERRUPT_ENABLE: u8 = 1<<7;
pub const ENABLE: u8 = 1<<6; pub const ENABLE: u8 = 1<<6;
pub const DATA_ORDER_LSB: u8 = 1<<5; pub const DATA_ORDER_LSB: u8 = 1<<5;
@ -155,7 +151,7 @@ mod spcr {
/// Constants for the status register. /// Constants for the status register.
#[allow(dead_code)] #[allow(dead_code)]
mod spsr { mod status_register {
/// SPI interrupt flag. /// SPI interrupt flag.
pub const SPIF: u8 = 1<<7; pub const SPIF: u8 = 1<<7;
/// Write collision flag. /// Write collision flag.