From aecd4edb360a5d6508e01f457af5de0ac577f20e Mon Sep 17 00:00:00 2001 From: Dylan McKay Date: Mon, 5 Nov 2018 23:05:34 +1300 Subject: [PATCH] Rename Mask to RegisterBits This is much more intuitive. --- core_generator/build.rs | 3 +- core_generator/gen.rs | 34 +++++----- src/lib.rs | 2 +- src/modules/spi/mod.rs | 32 +++++----- src/modules/timer/timer16.rs | 85 ++++++++++++------------- src/modules/timer/timer8.rs | 60 +++++++++--------- src/pin.rs | 15 +++-- src/register.rs | 116 ++++++++++++++++++++++------------- 8 files changed, 191 insertions(+), 156 deletions(-) diff --git a/core_generator/build.rs b/core_generator/build.rs index d9d94cd..e148399 100644 --- a/core_generator/build.rs +++ b/core_generator/build.rs @@ -52,6 +52,7 @@ fn generate_config_module() -> Result<(), io::Error> { let mut f = File::create(&path)?; let clock = env!("AVR_CPU_FREQUENCY_HZ"); + writeln!(f, "/// The clock frequency of device being targeted in Hertz.")?; writeln!(f, "pub const CPU_FREQUENCY_HZ: u32 = {};", clock)?; Ok(()) } @@ -81,7 +82,7 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> { fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { writeln!(w, "//! Core for {}.", mcu.device.name)?; writeln!(w)?; - writeln!(w, "use {{Mask, Register}};")?; + writeln!(w, "use {{RegisterBits, Register}};")?; writeln!(w, "use modules;")?; writeln!(w)?; diff --git a/core_generator/gen.rs b/core_generator/gen.rs index a4b23cf..4b0d4da 100644 --- a/core_generator/gen.rs +++ b/core_generator/gen.rs @@ -15,7 +15,7 @@ pub fn write_registers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { writeln!(w, "impl {} {{", register.name)?; for bitfield in register.bitfields.iter() { // Create a mask for the whole bitset. - writeln!(w, " pub const {}: Mask = Mask::new(0x{:x});", bitfield.name, bitfield.mask)?; + writeln!(w, " pub const {}: RegisterBits = RegisterBits::new(0x{:x});", bitfield.name, bitfield.mask)?; // We create masks for the individual bits in the field if there // is more than one bit in the field. @@ -23,7 +23,7 @@ pub fn write_registers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { let mut current_mask_bit_num = 0; for current_register_bit_num in 0..15 { if (current_mask & 0b1) == 0b1 { - writeln!(w, " pub const {}{}: Mask = Mask::new(1<<{});", + writeln!(w, " pub const {}{}: RegisterBits = RegisterBits::new(1<<{});", bitfield.name, current_mask_bit_num, current_register_bit_num)?; current_mask_bit_num += 1; } @@ -182,13 +182,13 @@ pub fn write_timers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?; writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?; writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?; - writeln!(w, " const CS0: Mask = Self::ControlB::CS00;")?; - writeln!(w, " const CS1: Mask = Self::ControlB::CS01;")?; - writeln!(w, " const CS2: Mask = Self::ControlB::CS02;")?; - writeln!(w, " const WGM0: Mask = Self::ControlA::WGM00;")?; - writeln!(w, " const WGM1: Mask = Self::ControlA::WGM01;")?; - writeln!(w, " const WGM2: Mask = Self::ControlB::WGM020;")?; - writeln!(w, " const OCIEA: Mask = Self::InterruptMask::OCIE{}A;", timer_number)?; + writeln!(w, " const CS0: RegisterBits = Self::ControlB::CS00;")?; + writeln!(w, " const CS1: RegisterBits = Self::ControlB::CS01;")?; + writeln!(w, " const CS2: RegisterBits = Self::ControlB::CS02;")?; + writeln!(w, " const WGM0: RegisterBits = Self::ControlA::WGM00;")?; + writeln!(w, " const WGM1: RegisterBits = Self::ControlA::WGM01;")?; + writeln!(w, " const WGM2: RegisterBits = Self::ControlB::WGM020;")?; + writeln!(w, " const OCIEA: RegisterBits = Self::InterruptMask::OCIE{}A;", timer_number)?; writeln!(w, "}}")?; } @@ -218,14 +218,14 @@ pub fn write_timers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?; writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?; writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?; - writeln!(w, " const CS0: Mask = Self::ControlB::CS10;")?; - writeln!(w, " const CS1: Mask = Self::ControlB::CS11;")?; - writeln!(w, " const CS2: Mask = Self::ControlB::CS12;")?; - writeln!(w, " const WGM0: Mask = Self::ControlA::WGM10;")?; - writeln!(w, " const WGM1: Mask = Self::ControlA::WGM11;")?; - writeln!(w, " const WGM2: Mask = Self::ControlB::WGM10;")?; - writeln!(w, " const WGM3: Mask = Self::ControlB::WGM11;")?; - writeln!(w, " const OCIEA: Mask = Self::InterruptMask::OCIE{}A;", timer_number)?; + writeln!(w, " const CS0: RegisterBits = Self::ControlB::CS10;")?; + writeln!(w, " const CS1: RegisterBits = Self::ControlB::CS11;")?; + writeln!(w, " const CS2: RegisterBits = Self::ControlB::CS12;")?; + writeln!(w, " const WGM0: RegisterBits = Self::ControlA::WGM10;")?; + writeln!(w, " const WGM1: RegisterBits = Self::ControlA::WGM11;")?; + writeln!(w, " const WGM2: RegisterBits = Self::ControlB::WGM10;")?; + writeln!(w, " const WGM3: RegisterBits = Self::ControlB::WGM11;")?; + writeln!(w, " const OCIEA: RegisterBits = Self::InterruptMask::OCIE{}A;", timer_number)?; writeln!(w, "}}")?; } diff --git a/src/lib.rs b/src/lib.rs index 1089a3b..6825751 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -14,7 +14,7 @@ #![no_std] -pub use self::register::{Mask, Register, RegisterValue}; +pub use self::register::{Register, RegisterBits, RegisterValue}; pub use self::pin::{DataDirection, Pin}; pub mod prelude; diff --git a/src/modules/spi/mod.rs b/src/modules/spi/mod.rs index e6cdbd1..73dac79 100644 --- a/src/modules/spi/mod.rs +++ b/src/modules/spi/mod.rs @@ -56,87 +56,87 @@ pub trait HardwareSpi { /// Sets the clock speed. fn set_clock(clock: u32) { let mask = clock::ClockMask::with_clock(clock); - Self::ControlRegister::set_raw(mask.control_register_mask()); - Self::StatusRegister::set_raw(mask.status_register_mask()); + Self::ControlRegister::set_mask_raw(mask.control_register_mask()); + Self::StatusRegister::set_mask_raw(mask.status_register_mask()); } /// Enables interrupts for the spi module. #[inline(always)] fn enable_interrupt() { - Self::ControlRegister::set_raw(settings::control_register::INTERRUPT_ENABLE); + Self::ControlRegister::set_mask_raw(settings::control_register::INTERRUPT_ENABLE); } /// Disables interrupts for the spi module. #[inline(always)] fn disable_interrupt() { - Self::ControlRegister::unset_raw(settings::control_register::INTERRUPT_ENABLE); + Self::ControlRegister::unset_mask_raw(settings::control_register::INTERRUPT_ENABLE); } /// Enables the SPI. #[inline(always)] fn enable() { - Self::ControlRegister::set_raw(settings::control_register::ENABLE); + Self::ControlRegister::set_mask_raw(settings::control_register::ENABLE); } /// Disables the SPI. #[inline(always)] fn disable() { - Self::ControlRegister::unset_raw(settings::control_register::ENABLE); + Self::ControlRegister::unset_mask_raw(settings::control_register::ENABLE); } /// Enables least-significant-bit first. #[inline(always)] fn set_lsb() { - Self::ControlRegister::set_raw(settings::control_register::DATA_ORDER_LSB); + Self::ControlRegister::set_mask_raw(settings::control_register::DATA_ORDER_LSB); } /// Enables most-significant-bit first. #[inline(always)] fn set_msb() { - Self::ControlRegister::unset_raw(settings::control_register::DATA_ORDER_LSB); + Self::ControlRegister::unset_mask_raw(settings::control_register::DATA_ORDER_LSB); } /// Enables master mode. #[inline(always)] fn set_master() { - Self::ControlRegister::set_raw(settings::control_register::MASTER); + Self::ControlRegister::set_mask_raw(settings::control_register::MASTER); } /// Enables slave mode. #[inline(always)] fn set_slave() { - Self::ControlRegister::unset_raw(settings::control_register::MASTER); + Self::ControlRegister::unset_mask_raw(settings::control_register::MASTER); } /// Enables double speed mode. #[inline(always)] fn enable_double_speed() { - Self::StatusRegister::set_raw(settings::status_register::SPI2X); + Self::StatusRegister::set_mask_raw(settings::status_register::SPI2X); } /// Disables double speed mode. #[inline(always)] fn disable_double_speed() { - Self::StatusRegister::unset_raw(settings::status_register::SPI2X); + Self::StatusRegister::unset_mask_raw(settings::status_register::SPI2X); } /// Checks if there is a write collision. #[inline(always)] fn is_write_collision() -> bool { - Self::StatusRegister::is_set_raw(settings::status_register::WCOL) + Self::StatusRegister::is_mask_set_raw(settings::status_register::WCOL) } /// Sends a byte through the serial. #[inline(always)] fn send_byte(byte: u8) { Self::DataRegister::write(byte); - Self::StatusRegister::wait_until_set_raw(settings::status_register::SPIF); + Self::StatusRegister::wait_until_mask_set_raw(settings::status_register::SPIF); } /// Reads a byte from the serial. #[inline(always)] fn receive_byte() -> u8 { - Self::StatusRegister::wait_until_set_raw(settings::status_register::SPIF); + Self::StatusRegister::wait_until_mask_set_raw(settings::status_register::SPIF); Self::DataRegister::read() } @@ -144,7 +144,7 @@ pub trait HardwareSpi { #[inline(always)] fn send_receive(byte: u8) -> u8 { Self::DataRegister::write(byte); - Self::StatusRegister::wait_until_set_raw(settings::status_register::SPIF); + Self::StatusRegister::wait_until_mask_set_raw(settings::status_register::SPIF); Self::DataRegister::read() } } diff --git a/src/modules/timer/timer16.rs b/src/modules/timer/timer16.rs index 4dce3ab..961f75b 100644 --- a/src/modules/timer/timer16.rs +++ b/src/modules/timer/timer16.rs @@ -1,4 +1,4 @@ -use {Mask, Register}; +use {RegisterBits, Register}; use core::marker; /// A 16-bit timer. @@ -41,16 +41,16 @@ pub trait Timer16 : Sized { /// For example, TIFR0. type InterruptFlag: Register; - const CS0: Mask; - const CS1: Mask; - const CS2: Mask; + const CS0: RegisterBits; + const CS1: RegisterBits; + const CS2: RegisterBits; - const WGM0: Mask; - const WGM1: Mask; - const WGM2: Mask; - const WGM3: Mask; + const WGM0: RegisterBits; + const WGM1: RegisterBits; + const WGM2: RegisterBits; + const WGM3: RegisterBits; - const OCIEA: Mask; + const OCIEA: RegisterBits; fn setup() -> Timer16Setup { Timer16Setup::new() } } @@ -67,23 +67,23 @@ pub enum ClockSource { } impl ClockSource { - fn bits(&self) -> Mask { + fn bits(&self) -> RegisterBits { use self::ClockSource::*; match *self { - None => Mask::zero() | Mask::zero() | Mask::zero(), - Prescale1 => Mask::zero() | Mask::zero() | T::CS0, - Prescale8 => Mask::zero() | T::CS1 | Mask::zero(), - Prescale64 => Mask::zero() | T::CS1 | T::CS0, - Prescale256 => T::CS2 | Mask::zero() | Mask::zero(), - Prescale1024 => T::CS2 | Mask::zero() | T::CS0, - ExternalFalling => T::CS2 | T::CS1 | Mask::zero(), + None => RegisterBits::zero() | RegisterBits::zero() | RegisterBits::zero(), + Prescale1 => RegisterBits::zero() | RegisterBits::zero() | T::CS0, + Prescale8 => RegisterBits::zero() | T::CS1 | RegisterBits::zero(), + Prescale64 => RegisterBits::zero() | T::CS1 | T::CS0, + Prescale256 => T::CS2 | RegisterBits::zero() | RegisterBits::zero(), + Prescale1024 => T::CS2 | RegisterBits::zero() | T::CS0, + ExternalFalling => T::CS2 | T::CS1 | RegisterBits::zero(), ExternalRising => T::CS2 | T::CS1 | T::CS0, } } #[inline] - fn mask() -> Mask { + fn mask() -> RegisterBits { !(T::CS2 | T::CS1 | T::CS0) } } @@ -109,45 +109,46 @@ pub enum WaveformGenerationMode { impl WaveformGenerationMode { /// Returns bits for TCCR1A, TCCR1B #[inline] - fn bits(&self) -> (Mask, Mask) { + fn bits(&self) -> (RegisterBits, RegisterBits) { use self::WaveformGenerationMode::*; + use RegisterBits as B; // It makes more sense to return bytes (A,B), but the manual // lists the table as (B,A). We match the manual here for // inspection purposes and flip the values for sanity // purposes. let (b, a) = match *self { - Normal => (Mask::zero() | Mask::zero(), Mask::zero() | Mask::zero()), - PwmPhaseCorrect8Bit => (Mask::zero() | Mask::zero(), Mask::zero() | T::WGM0), - PwmPhaseCorrect9Bit => (Mask::zero() | Mask::zero(), T::WGM1 | Mask::zero()), - PwmPhaseCorrect10Bit => (Mask::zero() | Mask::zero(), T::WGM1 | T::WGM0), - ClearOnTimerMatchOutputCompare => (Mask::zero() | T::WGM2, Mask::zero() | Mask::zero()), - FastPwm8Bit => (Mask::zero() | T::WGM2, Mask::zero() | T::WGM0), - FastPwm9Bit => (Mask::zero() | T::WGM2, T::WGM1 | Mask::zero()), - FastPwm10Bit => (Mask::zero() | T::WGM2, T::WGM1 | T::WGM0), - PwmPhaseAndFrequencyCorrectInputCapture => (T::WGM3 | Mask::zero(), Mask::zero() | Mask::zero()), - PwmPhaseAndFrequencyCorrectOutputCompare => (T::WGM3 | Mask::zero(), Mask::zero() | T::WGM0), - PwmPhaseCorrectInputCapture => (T::WGM3 | Mask::zero(), T::WGM1 | Mask::zero()), - PwmPhaseCorrectOutputCompare => (T::WGM3 | Mask::zero(), T::WGM1 | T::WGM0), - ClearOnTimerMatchInputCapture => (T::WGM3 | T::WGM2, Mask::zero() | Mask::zero()), - // Reserved => (T::WGM3 | T::WGM2, Mask::zero() | T::WGM0), - FastPwmInputCapture => (T::WGM3 | T::WGM2, T::WGM1 | Mask::zero()), - FastPwmOutputCompare => (T::WGM3 | T::WGM2, T::WGM1 | T::WGM0), + Normal => (B::zero() | B::zero(), B::zero() | B::zero()), + PwmPhaseCorrect8Bit => (B::zero() | B::zero(), B::zero() | T::WGM0), + PwmPhaseCorrect9Bit => (B::zero() | B::zero(), T::WGM1 | B::zero()), + PwmPhaseCorrect10Bit => (B::zero() | B::zero(), T::WGM1 | T::WGM0), + ClearOnTimerMatchOutputCompare => (B::zero() | T::WGM2, B::zero() | B::zero()), + FastPwm8Bit => (B::zero() | T::WGM2, B::zero() | T::WGM0), + FastPwm9Bit => (B::zero() | T::WGM2, T::WGM1 | B::zero()), + FastPwm10Bit => (B::zero() | T::WGM2, T::WGM1 | T::WGM0), + PwmPhaseAndFrequencyCorrectInputCapture => (T::WGM3 | B::zero(), B::zero() | B::zero()), + PwmPhaseAndFrequencyCorrectOutputCompare => (T::WGM3 | B::zero(), B::zero() | T::WGM0), + PwmPhaseCorrectInputCapture => (T::WGM3 | B::zero(), T::WGM1 | B::zero()), + PwmPhaseCorrectOutputCompare => (T::WGM3 | B::zero(), T::WGM1 | T::WGM0), + ClearOnTimerMatchInputCapture => (T::WGM3 | T::WGM2, B::zero() | B::zero()), + // Reserved => (T::WGM3 | T::WGM2, B::zero() | T::WGM0), + FastPwmInputCapture => (T::WGM3 | T::WGM2, T::WGM1 | B::zero()), + FastPwmOutputCompare => (T::WGM3 | T::WGM2, T::WGM1 | T::WGM0), }; (a, b) } #[inline] - fn mask() -> (Mask, Mask) { + fn mask() -> (RegisterBits, RegisterBits) { (!(T::WGM0 | T::WGM1), !(T::WGM2 | T::WGM3)) } } pub struct Timer16Setup { - a: Mask, - b: Mask, - c: Mask, + a: RegisterBits, + b: RegisterBits, + c: RegisterBits, output_compare_1: Option, _phantom: marker::PhantomData, } @@ -156,9 +157,9 @@ impl Timer16Setup { #[inline] fn new() -> Self { Timer16Setup { - a: Mask::zero(), - b: Mask::zero(), - c: Mask::zero(), + a: RegisterBits::zero(), + b: RegisterBits::zero(), + c: RegisterBits::zero(), output_compare_1: None, _phantom: marker::PhantomData, } diff --git a/src/modules/timer/timer8.rs b/src/modules/timer/timer8.rs index 15bfb98..a02f6d5 100644 --- a/src/modules/timer/timer8.rs +++ b/src/modules/timer/timer8.rs @@ -1,4 +1,4 @@ -use {Mask, Register}; +use {RegisterBits, Register}; use core::marker; /// A 8-bit timer. @@ -37,21 +37,21 @@ pub trait Timer8 : Sized { type InterruptFlag: Register; /// Bit 0 of the clock select mask. - const CS0: Mask; + const CS0: RegisterBits; /// Bit 1 of the clock select mask. - const CS1: Mask; + const CS1: RegisterBits; /// Bit 2 of the clock select mask. - const CS2: Mask; + const CS2: RegisterBits; /// Bit 0 of the waveform generation mode mask. - const WGM0: Mask; + const WGM0: RegisterBits; /// Bit 1 of the waveform generation mode mask. - const WGM1: Mask; + const WGM1: RegisterBits; /// Bit 2 of the waveform generation mode mask. - const WGM2: Mask; + const WGM2: RegisterBits; /// Output compare interrupt enable flag. - const OCIEA: Mask; + const OCIEA: RegisterBits; } pub enum ClockSource { @@ -66,23 +66,23 @@ pub enum ClockSource { } impl ClockSource { - fn bits(&self) -> Mask { + fn bits(&self) -> RegisterBits { use self::ClockSource::*; match *self { - None => Mask::zero() | Mask::zero() | Mask::zero(), - Prescale1 => Mask::zero() | Mask::zero() | T::CS0, - Prescale8 => Mask::zero() | T::CS1 | Mask::zero(), - Prescale64 => Mask::zero() | T::CS1 | T::CS0, - Prescale256 => T::CS2 | Mask::zero() | Mask::zero(), - Prescale1024 => T::CS2 | Mask::zero() | T::CS0, - ExternalFalling => T::CS2 | T::CS1 | Mask::zero(), + None => RegisterBits::zero() | RegisterBits::zero() | RegisterBits::zero(), + Prescale1 => RegisterBits::zero() | RegisterBits::zero() | T::CS0, + Prescale8 => RegisterBits::zero() | T::CS1 | RegisterBits::zero(), + Prescale64 => RegisterBits::zero() | T::CS1 | T::CS0, + Prescale256 => T::CS2 | RegisterBits::zero() | RegisterBits::zero(), + Prescale1024 => T::CS2 | RegisterBits::zero() | T::CS0, + ExternalFalling => T::CS2 | T::CS1 | RegisterBits::zero(), ExternalRising => T::CS2 | T::CS1 | T::CS0, } } #[inline] - fn mask() -> Mask { + fn mask() -> RegisterBits { !(T::CS2 | T::CS1 | T::CS0) } } @@ -99,7 +99,7 @@ pub enum WaveformGenerationMode { impl WaveformGenerationMode { /// Returns bits for TCCR0A, TCCR0B #[inline] - fn bits(&self) -> (Mask, Mask) { + fn bits(&self) -> (RegisterBits, RegisterBits) { use self::WaveformGenerationMode::*; // It makes more sense to return bytes (A,B), but the manual @@ -107,13 +107,13 @@ impl WaveformGenerationMode { // inspection purposes and flip the values for sanity // purposes. let (b, a) = match *self { - Normal => (Mask::zero(), Mask::zero() | Mask::zero()), - PwmPhaseCorrect => (Mask::zero(), Mask::zero() | T::WGM0), - ClearOnTimerMatchOutputCompare => (Mask::zero(), T::WGM1 | Mask::zero()), - FastPwm => (Mask::zero(), T::WGM1 | T::WGM0), - // Reserved => (T::WGM2, Mask::zero() | Mask::zero()), - PwmPhaseCorrectOutputCompare => (T::WGM2, Mask::zero() | T::WGM0), - // Reserved => (T::WGM2, T::WGM1 | Mask::zero())), + Normal => (RegisterBits::zero(), RegisterBits::zero() | RegisterBits::zero()), + PwmPhaseCorrect => (RegisterBits::zero(), RegisterBits::zero() | T::WGM0), + ClearOnTimerMatchOutputCompare => (RegisterBits::zero(), T::WGM1 | RegisterBits::zero()), + FastPwm => (RegisterBits::zero(), T::WGM1 | T::WGM0), + // Reserved => (T::WGM2, RegisterBits::zero() | RegisterBits::zero()), + PwmPhaseCorrectOutputCompare => (T::WGM2, RegisterBits::zero() | T::WGM0), + // Reserved => (T::WGM2, T::WGM1 | RegisterBits::zero())), FastPwmOutputCompare => (T::WGM2, T::WGM1 | T::WGM0), }; @@ -121,14 +121,14 @@ impl WaveformGenerationMode { } #[inline] - fn mask() -> (Mask, Mask) { + fn mask() -> (RegisterBits, RegisterBits) { (!(T::WGM0 | T::WGM1), !(T::WGM2)) } } pub struct Timer8Setup { - a: Mask, - b: Mask, + a: RegisterBits, + b: RegisterBits, output_compare_1: Option, _phantom: marker::PhantomData, } @@ -137,8 +137,8 @@ impl Timer8Setup { #[inline] pub fn new() -> Self { Timer8Setup { - a: Mask::zero(), - b: Mask::zero(), + a: RegisterBits::zero(), + b: RegisterBits::zero(), output_compare_1: None, _phantom: marker::PhantomData, } diff --git a/src/pin.rs b/src/pin.rs index c917721..806ba99 100644 --- a/src/pin.rs +++ b/src/pin.rs @@ -1,7 +1,10 @@ use Register; +/// Represents whether a pin is an input or an output. pub enum DataDirection { + /// The pin is exclusively used for reading signals. Input, + /// The pin is exclusively used for sending signals. Output, } @@ -11,7 +14,7 @@ pub trait Pin { type DDR: Register; /// The associated port register. type PORT: Register; - /// The associated pin register. + /// /// Reads from the register will read input bits. /// Writes to the register will toggle bits. @@ -31,13 +34,13 @@ pub trait Pin { /// Sets the pin up as an input. #[inline(always)] fn set_input() { - Self::DDR::unset_raw(Self::MASK); + Self::DDR::unset_mask_raw(Self::MASK); } /// Sets the pin up as an output. #[inline(always)] fn set_output() { - Self::DDR::set_raw(Self::MASK); + Self::DDR::set_mask_raw(Self::MASK); } /// Set the pin to high. @@ -45,7 +48,7 @@ pub trait Pin { /// The pin must be configured as an output. #[inline(always)] fn set_high() { - Self::PORT::set_raw(Self::MASK); + Self::PORT::set_mask_raw(Self::MASK); } /// Set the pin to low. @@ -53,7 +56,7 @@ pub trait Pin { /// The pin must be configured as an output. #[inline(always)] fn set_low() { - Self::PORT::unset_raw(Self::MASK); + Self::PORT::unset_mask_raw(Self::MASK); } /// Toggles the pin. @@ -72,7 +75,7 @@ pub trait Pin { /// The pin must be configured as an input. #[inline(always)] fn is_high() -> bool { - Self::PIN::is_set_raw(Self::MASK) + Self::PIN::is_mask_set_raw(Self::MASK) } /// Checks if the pin is currently low. diff --git a/src/register.rs b/src/register.rs index d642a80..2a13f98 100644 --- a/src/register.rs +++ b/src/register.rs @@ -1,6 +1,8 @@ use core::{cmp, convert, marker, ops}; /// A value that a register can store. +/// +/// All registers are either `u8` or `u16`. pub trait RegisterValue : Copy + Clone + ops::BitAnd + ops::BitAndAssign + @@ -16,8 +18,11 @@ pub trait RegisterValue : Copy + Clone + /// A register. pub trait Register : Sized { + /// The type that can represent the value of the register. type T: RegisterValue; - type Mask = Mask; + /// The type representing a set of bits that may be manipulated + /// within the register. + type RegisterBits = RegisterBits; /// The address of the register. const ADDRESS: *mut Self::T; @@ -36,35 +41,44 @@ pub trait Register : Sized { unsafe { *Self::ADDRESS } } - fn set(mask: Mask) { - Self::set_raw(mask.mask); + /// Sets a set of bits to `1` in the register. + fn set(bits: RegisterBits) { + Self::set_mask_raw(bits.mask); } /// Sets a bitmask in a register. /// /// This is equivalent to `r |= mask`. #[inline(always)] - fn set_raw(mask: Self::T) { + fn set_mask_raw(mask: Self::T) { unsafe { *Self::ADDRESS |= mask; } } - fn unset(mask: Mask) { - Self::unset_raw(mask.mask); + /// Unsets a set of bits in the register. + /// + /// All of the bits will be set to `0`. + fn unset(bits: RegisterBits) { + Self::unset_mask_raw(bits.mask); } /// Clears a bitmask from a register. /// /// This is equivalent to `r &= !mask`. #[inline(always)] - fn unset_raw(mask: Self::T) { + fn unset_mask_raw(mask: Self::T) { unsafe { *Self::ADDRESS &= !mask; } } - fn toggle(mask: Mask) { + /// Toggles a set of bits within the register. + /// + /// All specified bits which were previously `0` will become + /// `1`, and all specified bits that were previous `1` will + /// become `0`. + fn toggle(mask: RegisterBits) { Self::toggle_raw(mask.mask); } @@ -78,21 +92,29 @@ pub trait Register : Sized { } } - fn is_set(mask: Mask) -> bool { - Self::is_set_raw(mask.mask) + /// Checks if a set of bits are enabled. + /// + /// All specifed bits must be set for this function + /// to return `true`. + fn is_set(bits: RegisterBits) -> bool { + Self::is_mask_set_raw(bits.mask) } /// Checks if a mask is set in the register. /// /// This is equivalent to `(r & mask) == mask`. #[inline(always)] - fn is_set_raw(mask: Self::T) -> bool { + fn is_mask_set_raw(mask: Self::T) -> bool { unsafe { (*Self::ADDRESS & mask) == mask } } - fn is_clear(mask: Mask) -> bool { + /// Checks if a set of bits are not set. + /// + /// All specified bits must be `0` for this + /// function to return `true`. + fn is_clear(mask: RegisterBits) -> bool { Self::is_clear_raw(mask.mask) } @@ -106,92 +128,100 @@ pub trait Register : Sized { } } - /// Waits until some condition is true of the register. - #[inline(always)] - fn wait_until(mut f: F) - where F: FnMut() -> bool { - loop { - if f() { - break; - } - } + /// Waits until a set of bits are set in the register. + /// + /// This function will block until all bits that are set in + /// the mask are also set in the register. + fn wait_until_set(bits: RegisterBits) { + Self::wait_until_mask_set_raw(bits.mask); } - fn wait_until_set(mask: Mask) { - Self::wait_until_set_raw(mask.mask); - } - - /// Waits until a mask is set. + /// Waits until a bit mask is set in the register. + /// + /// This function will block until all bits that are set in + /// the mask are also set in the register. #[inline(always)] - fn wait_until_set_raw(mask: Self::T) { - Self::wait_until(|| Self::is_set_raw(mask)) + fn wait_until_mask_set_raw(mask: Self::T) { + wait_until(|| Self::is_mask_set_raw(mask)) } } -/// A register bitmask. +/// Represents a set of bits within a specific register. #[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)] -pub struct Mask { +pub struct RegisterBits { + /// The raw bitmask. mask: R::T, _phantom: marker::PhantomData, } -impl Mask where R: Register { +impl RegisterBits where R: Register { /// Creates a new register mask. pub const fn new(mask: R::T) -> Self { - Mask { mask, _phantom: marker::PhantomData } + RegisterBits { mask, _phantom: marker::PhantomData } } pub fn zero() -> Self { - Mask::new(0u8.into()) + RegisterBits::new(0u8.into()) } } -impl ops::BitOr for Mask where R: Register +impl ops::BitOr for RegisterBits where R: Register { type Output = Self; fn bitor(self, rhs: Self) -> Self { - Mask::new(self.mask | rhs.mask) + RegisterBits::new(self.mask | rhs.mask) } } -impl ops::BitOrAssign for Mask where R: Register { +impl ops::BitOrAssign for RegisterBits where R: Register { fn bitor_assign(&mut self, rhs: Self) { self.mask |= rhs.mask; } } -impl ops::BitAnd for Mask where R: Register +impl ops::BitAnd for RegisterBits where R: Register { type Output = Self; fn bitand(self, rhs: Self) -> Self { - Mask::new(self.mask & rhs.mask) + RegisterBits::new(self.mask & rhs.mask) } } -impl ops::BitAndAssign for Mask where R: Register { +impl ops::BitAndAssign for RegisterBits where R: Register { fn bitand_assign(&mut self, rhs: Self) { self.mask &= rhs.mask; } } -impl ops::Not for Mask where R: Register { +impl ops::Not for RegisterBits where R: Register { type Output = Self; fn not(self) -> Self { - Mask::new(!self.mask) + RegisterBits::new(!self.mask) } } -impl Into for Mask where R: Register { +impl Into for RegisterBits where R: Register { fn into(self) -> u8 { self.mask } } -impl Into for Mask where R: Register { +impl Into for RegisterBits where R: Register { fn into(self) -> u16 { self.mask } } impl RegisterValue for u8 { } impl RegisterValue for u16 { } +/// Waits until some condition is true of the register. +#[inline(always)] +fn wait_until(mut f: F) + where F: FnMut() -> bool { + loop { + if f() { + break; + } + } +} +