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Make a module public

This commit is contained in:
Dylan McKay 2017-08-31 02:24:24 +12:00
parent fcca0f8c27
commit f1756787db
3 changed files with 6 additions and 6 deletions
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3
build.rs
View File

@ -53,7 +53,8 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
writeln!(w, "//! Core for {}.", mcu.device.name)?;
writeln!(w)?;
writeln!(w, "use {{HardwareSpi, HardwareUsart, Register}};")?;
writeln!(w, "use {{HardwareUsart, Register}};")?;
writeln!(w, "use spi::HardwareSpi;")?;
writeln!(w)?;
gen::write_registers(mcu, w)?;

4
src/lib.rs
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@ -10,7 +10,6 @@
pub use self::reg::Register;
pub use self::pin::Pin;
pub use self::spi::HardwareSpi;
pub use self::usart::HardwareUsart;
pub mod prelude;
@ -19,9 +18,10 @@ pub mod timer0;
pub mod timer1;
pub mod cores;
pub mod spi;
mod reg;
mod pin;
mod spi;
mod usart;
pub enum DataDirection {

5
src/spi.rs
View File

@ -133,8 +133,7 @@ pub trait HardwareSpi {
}
/// Constants for the control register.
#[allow(dead_code)]
mod control_register {
pub mod control_register {
pub const INTERRUPT_ENABLE: u8 = 1<<7;
pub const ENABLE: u8 = 1<<6;
pub const DATA_ORDER_LSB: u8 = 1<<5;
@ -151,7 +150,7 @@ mod control_register {
/// Constants for the status register.
#[allow(dead_code)]
mod status_register {
pub mod status_register {
/// SPI interrupt flag.
pub const SPIF: u8 = 1<<7;
/// Write collision flag.