Make a module public
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fcca0f8c27
commit
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3
build.rs
3
build.rs
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@ -53,7 +53,8 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
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fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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writeln!(w, "//! Core for {}.", mcu.device.name)?;
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writeln!(w)?;
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writeln!(w, "use {{HardwareSpi, HardwareUsart, Register}};")?;
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writeln!(w, "use {{HardwareUsart, Register}};")?;
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writeln!(w, "use spi::HardwareSpi;")?;
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writeln!(w)?;
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gen::write_registers(mcu, w)?;
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@ -10,7 +10,6 @@
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pub use self::reg::Register;
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pub use self::pin::Pin;
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pub use self::spi::HardwareSpi;
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pub use self::usart::HardwareUsart;
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pub mod prelude;
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@ -19,9 +18,10 @@ pub mod timer0;
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pub mod timer1;
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pub mod cores;
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pub mod spi;
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mod reg;
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mod pin;
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mod spi;
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mod usart;
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pub enum DataDirection {
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@ -133,8 +133,7 @@ pub trait HardwareSpi {
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}
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/// Constants for the control register.
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#[allow(dead_code)]
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mod control_register {
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pub mod control_register {
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pub const INTERRUPT_ENABLE: u8 = 1<<7;
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pub const ENABLE: u8 = 1<<6;
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pub const DATA_ORDER_LSB: u8 = 1<<5;
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@ -151,7 +150,7 @@ mod control_register {
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/// Constants for the status register.
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#[allow(dead_code)]
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mod status_register {
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pub mod status_register {
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/// SPI interrupt flag.
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pub const SPIF: u8 = 1<<7;
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/// Write collision flag.
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