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Rename MISO/MOSI to SerialDataIn and SerialDataOut

This commit is contained in:
Savanni D'Gerinel 2023-04-02 11:35:35 -04:00
parent d2b11bceb8
commit f516e1216b
17 changed files with 267 additions and 146 deletions
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220
core_generator/src/gen.rs
View File

@ -7,7 +7,9 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
let ty = if register.size == 1 { "u8" } else { "u16" };
// HACK: Skip, atmeg328p pack defines two of these.
if register.name == "GTCCR" { continue; }
if register.name == "GTCCR" {
continue;
}
writeln!(w, "#[allow(non_camel_case_types)]")?;
writeln!(w, "pub struct {};", register.name)?;
@ -16,7 +18,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
writeln!(w, "impl {} {{", register.name)?;
for bitfield in register.bitfields.iter() {
// Create a mask for the whole bitset.
writeln!(w, " pub const {}: RegisterBits<Self> = RegisterBits::new(0x{:x});", bitfield.name, bitfield.mask)?;
writeln!(
w,
" pub const {}: RegisterBits<Self> = RegisterBits::new(0x{:x});",
bitfield.name, bitfield.mask
)?;
// We create masks for the individual bits in the field if there
// is more than one bit in the field.
@ -24,8 +30,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
let mut current_mask_bit_num = 0;
for current_register_bit_num in 0..15 {
if (current_mask & 0b1) == 0b1 {
writeln!(w, " pub const {}{}: RegisterBits<Self> = RegisterBits::new(1<<{});",
bitfield.name, current_mask_bit_num, current_register_bit_num)?;
writeln!(
w,
" pub const {}{}: RegisterBits<Self> = RegisterBits::new(1<<{});",
bitfield.name, current_mask_bit_num, current_register_bit_num
)?;
current_mask_bit_num += 1;
}
@ -38,7 +47,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
writeln!(w, "impl Register for {} {{", register.name)?;
writeln!(w, " type T = {};", ty)?;
writeln!(w, " const ADDRESS: *mut {} = 0x{:x} as *mut {};", ty, register.offset, ty)?;
writeln!(
w,
" const ADDRESS: *mut {} = 0x{:x} as *mut {};",
ty, register.offset, ty
)?;
writeln!(w, "}}")?;
}
@ -61,9 +74,14 @@ pub fn write_pins(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
let idx = signal.index.expect("signal with no index");
let struct_name = format!("{}{}", port_letter, idx);
let io_module = mcu.modules.iter().find(|m| m.name == "PORT")
let io_module = mcu
.modules
.iter()
.find(|m| m.name == "PORT")
.expect("no port io module defined for this port");
let register_group = io_module.register_groups.iter()
let register_group = io_module
.register_groups
.iter()
.find(|rg| rg.name == instance.name)
.expect("no register group defined for this port");
@ -92,7 +110,9 @@ pub fn write_pins(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
pub fn write_spi_modules(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
if let Some(module) = mcu.module("SPI") {
let peripheral = mcu.peripheral("SPI").expect("found SPI module but no peripheral");
let peripheral = mcu
.peripheral("SPI")
.expect("found SPI module but no peripheral");
let port_peripheral = mcu.port_peripheral();
writeln!(w, "pub struct Spi;")?;
@ -100,16 +120,20 @@ pub fn write_spi_modules(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error>
writeln!(w, "impl modules::HardwareSpi for Spi {{")?;
for spi_signal in peripheral.signals() {
let spi_signal_name = spi_signal.group.clone().expect("spi signal does not have group name");
let (port_instance, port_signal) = port_peripheral.instance_signal_with_pad(&spi_signal.pad)
let spi_signal_name = spi_signal
.group
.clone()
.expect("spi signal does not have group name");
let (port_instance, port_signal) = port_peripheral
.instance_signal_with_pad(&spi_signal.pad)
.expect("no port signal associated with the spi signal pad");
let pin_name = self::pin_name(port_instance, port_signal);
let const_name = match &spi_signal_name[..] {
"MISO" => "MasterInSlaveOut",
"MOSI" => "MasterOutSlaveIn",
"MISO" => "SerialDataIn",
"MOSI" => "SerialDataOut",
"SCK" => "Clock",
"SS" => "SlaveSelect",
"SS" => "ChipSelect",
_ => panic!("unknown spi signal name: '{}'", spi_signal_name),
};
@ -140,12 +164,15 @@ pub fn write_usarts(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
writeln!(w)?;
writeln!(w, "impl modules::HardwareUsart for {} {{", usart.name)?;
for register in usart.registers.iter() {
let reg_ty = if register.name.starts_with("UDR") { // the data register.
let reg_ty = if register.name.starts_with("UDR") {
// the data register.
"DataRegister".to_owned()
} else if register.name.starts_with("UCSR") { // one of the three control/status registers.
} else if register.name.starts_with("UCSR") {
// one of the three control/status registers.
let suffix = register.name.chars().rev().next().unwrap();
format!("ControlRegister{}", suffix)
} else if register.name.starts_with("UBRR") { // the baud rate register.
} else if register.name.starts_with("UBRR") {
// the baud rate register.
"BaudRateRegister".to_owned()
} else {
panic!("unknown usart register '{}'", register.name);
@ -160,22 +187,30 @@ pub fn write_usarts(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
}
pub fn write_timers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
if let Some(tc) = mcu.module("TC8") { // Timer/Counter, 8-bit.
if let Some(tc) = mcu.module("TC8") {
// Timer/Counter, 8-bit.
const TYPE_NAME: &'static str = "Timer8";
let find_reg = |name: &'static str| {
tc.registers().find(|r| r.name.starts_with(name))
tc.registers()
.find(|r| r.name.starts_with(name))
.expect(&format!("could not find '{}' register", name))
};
let find_reg_suffix_optional = |name: &'static str, suffix: &'static str| {
tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
tc.registers()
.find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
};
let find_reg_suffix = |name: &'static str, suffix: &'static str| {
find_reg_suffix_optional(name, suffix)
.expect(&format!("could not find '{}' register", name))
};
let timer_number = find_reg("TIMSK").name.chars().last().unwrap()
.to_digit(10).unwrap();
let timer_number = find_reg("TIMSK")
.name
.chars()
.last()
.unwrap()
.to_digit(10)
.unwrap();
// TODO: At the moment, we do not support 8 bit timers that don't have two compare
// registers.
@ -186,58 +221,145 @@ pub fn write_timers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
writeln!(w, "pub struct {};", TYPE_NAME)?;
writeln!(w)?;
writeln!(w, "impl modules::Timer8 for {} {{", TYPE_NAME)?;
writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
writeln!(
w,
" type CompareA = {};",
find_reg_suffix("OCR", "A").name
)?;
writeln!(
w,
" type CompareB = {};",
find_reg_suffix("OCR", "B").name
)?;
writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
writeln!(
w,
" type ControlA = {};",
find_reg_suffix("TCCR", "A").name
)?;
writeln!(
w,
" type ControlB = {};",
find_reg_suffix("TCCR", "B").name
)?;
writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
writeln!(w, " const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS00;")?;
writeln!(w, " const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS01;")?;
writeln!(w, " const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS02;")?;
writeln!(w, " const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM00;")?;
writeln!(w, " const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM01;")?;
writeln!(w, " const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM020;")?;
writeln!(
w,
" const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS00;"
)?;
writeln!(
w,
" const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS01;"
)?;
writeln!(
w,
" const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS02;"
)?;
writeln!(
w,
" const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM00;"
)?;
writeln!(
w,
" const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM01;"
)?;
writeln!(
w,
" const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM020;"
)?;
writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
writeln!(w, "}}")?;
}
}
if let Some(tc) = mcu.module("TC16") { // Timer/Counter, 16-bit.
if let Some(tc) = mcu.module("TC16") {
// Timer/Counter, 16-bit.
const TYPE_NAME: &'static str = "Timer16";
let find_reg = |name: &'static str| {
tc.registers().find(|r| r.name.starts_with(name))
tc.registers()
.find(|r| r.name.starts_with(name))
.expect(&format!("could not find '{}' register", name))
};
let find_reg_suffix = |name: &'static str, suffix: &'static str| {
tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
tc.registers()
.find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
.expect(&format!("could not find '{}' register", name))
};
let timer_number = find_reg("TIMSK").name.chars().last().unwrap()
.to_digit(10).unwrap();
let timer_number = find_reg("TIMSK")
.name
.chars()
.last()
.unwrap()
.to_digit(10)
.unwrap();
writeln!(w, "/// 16-bit timer.")?;
writeln!(w, "pub struct {};", TYPE_NAME)?;
writeln!(w)?;
writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?;
writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
writeln!(
w,
" type CompareA = {};",
find_reg_suffix("OCR", "A").name
)?;
writeln!(
w,
" type CompareB = {};",
find_reg_suffix("OCR", "B").name
)?;
writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?;
writeln!(
w,
" type ControlA = {};",
find_reg_suffix("TCCR", "A").name
)?;
writeln!(
w,
" type ControlB = {};",
find_reg_suffix("TCCR", "B").name
)?;
writeln!(
w,
" type ControlC = {};",
find_reg_suffix("TCCR", "C").name
)?;
writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
writeln!(w, " const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS10;")?;
writeln!(w, " const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS11;")?;
writeln!(w, " const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS12;")?;
writeln!(w, " const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM10;")?;
writeln!(w, " const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM11;")?;
writeln!(w, " const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM10;")?;
writeln!(w, " const WGM3: RegisterBits<Self::ControlB> = Self::ControlB::WGM11;")?;
writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
writeln!(
w,
" const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS10;"
)?;
writeln!(
w,
" const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS11;"
)?;
writeln!(
w,
" const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS12;"
)?;
writeln!(
w,
" const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM10;"
)?;
writeln!(
w,
" const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM11;"
)?;
writeln!(
w,
" const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM10;"
)?;
writeln!(
w,
" const WGM3: RegisterBits<Self::ControlB> = Self::ControlB::WGM11;"
)?;
writeln!(
w,
" const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;",
timer_number
)?;
writeln!(w, "}}")?;
}

6
src/cores/atmega168.rs
View File

@ -1791,9 +1791,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega168a.rs
View File

@ -1794,9 +1794,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega168p.rs
View File

@ -1800,9 +1800,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega168pa.rs
View File

@ -1800,9 +1800,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega328.rs
View File

@ -2040,9 +2040,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega328p.rs
View File

@ -1800,9 +1800,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega48.rs
View File

@ -1773,9 +1773,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega48a.rs
View File

@ -1798,9 +1798,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega48p.rs
View File

@ -1779,9 +1779,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega48pa.rs
View File

@ -1804,9 +1804,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega88.rs
View File

@ -1791,9 +1791,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega88a.rs
View File

@ -1794,9 +1794,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega88p.rs
View File

@ -1797,9 +1797,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega88pa.rs
View File

@ -1800,9 +1800,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

78
src/cores/mod.rs
View File

@ -1,40 +1,46 @@
//! The primary module containing microcontroller-specific core definitions
/// The ATmega88.
#[cfg(any(avr_mcu_atmega88, feature = "all-mcus"))] pub mod atmega88;
#[cfg(avr_mcu_atmega88)] pub use self::atmega88 as current;
/// The ATmega48A.
#[cfg(any(avr_mcu_atmega48a, feature = "all-mcus"))] pub mod atmega48a;
#[cfg(avr_mcu_atmega48a)] pub use self::atmega48a as current;
/// The ATmega168A.
#[cfg(any(avr_mcu_atmega168a, feature = "all-mcus"))] pub mod atmega168a;
#[cfg(avr_mcu_atmega168a)] pub use self::atmega168a as current;
/// The ATmega88P.
#[cfg(any(avr_mcu_atmega88p, feature = "all-mcus"))] pub mod atmega88p;
#[cfg(avr_mcu_atmega88p)] pub use self::atmega88p as current;
/// The ATmega168P.
#[cfg(any(avr_mcu_atmega168p, feature = "all-mcus"))] pub mod atmega168p;
#[cfg(avr_mcu_atmega168p)] pub use self::atmega168p as current;
/// The ATmega88PA.
#[cfg(any(avr_mcu_atmega88pa, feature = "all-mcus"))] pub mod atmega88pa;
#[cfg(avr_mcu_atmega88pa)] pub use self::atmega88pa as current;
/// The ATmega168.
#[cfg(any(avr_mcu_atmega168, feature = "all-mcus"))] pub mod atmega168;
#[cfg(avr_mcu_atmega168)] pub use self::atmega168 as current;
/// The ATmega48PA.
#[cfg(any(avr_mcu_atmega48pa, feature = "all-mcus"))] pub mod atmega48pa;
#[cfg(avr_mcu_atmega48pa)] pub use self::atmega48pa as current;
/// The ATmega328P.
#[cfg(any(avr_mcu_atmega328p, feature = "all-mcus"))] pub mod atmega328p;
#[cfg(avr_mcu_atmega328p)] pub use self::atmega328p as current;
/// The ATmega48PA.
#[cfg(any(avr_mcu_atmega48pa, feature = "all-mcus"))] pub mod atmega48pa;
#[cfg(avr_mcu_atmega48pa)] pub use self::atmega48pa as current;
/// The ATmega88.
#[cfg(any(avr_mcu_atmega88, feature = "all-mcus"))] pub mod atmega88;
#[cfg(avr_mcu_atmega88)] pub use self::atmega88 as current;
/// The ATmega168A.
#[cfg(any(avr_mcu_atmega168a, feature = "all-mcus"))] pub mod atmega168a;
#[cfg(avr_mcu_atmega168a)] pub use self::atmega168a as current;
/// The ATmega48.
#[cfg(any(avr_mcu_atmega48, feature = "all-mcus"))] pub mod atmega48;
#[cfg(avr_mcu_atmega48)] pub use self::atmega48 as current;
/// The ATmega48A.
#[cfg(any(avr_mcu_atmega48a, feature = "all-mcus"))] pub mod atmega48a;
#[cfg(avr_mcu_atmega48a)] pub use self::atmega48a as current;
/// The ATmega88PA.
#[cfg(any(avr_mcu_atmega88pa, feature = "all-mcus"))] pub mod atmega88pa;
#[cfg(avr_mcu_atmega88pa)] pub use self::atmega88pa as current;
/// The ATmega328.
///
/// This device is chosen as the default when the crate is targeting non-AVR devices.
#[cfg(any(avr_mcu_atmega328, feature = "all-mcus", not(target_arch = "avr")))] pub mod atmega328;
#[cfg(any(avr_mcu_atmega328, not(target_arch = "avr")))] pub use self::atmega328 as current;
/// The ATmega168P.
#[cfg(any(avr_mcu_atmega168p, feature = "all-mcus"))] pub mod atmega168p;
#[cfg(avr_mcu_atmega168p)] pub use self::atmega168p as current;
/// The ATmega88P.
#[cfg(any(avr_mcu_atmega88p, feature = "all-mcus"))] pub mod atmega88p;
#[cfg(avr_mcu_atmega88p)] pub use self::atmega88p as current;
/// The ATmega168PA.
#[cfg(any(avr_mcu_atmega168pa, feature = "all-mcus"))] pub mod atmega168pa;
@ -44,18 +50,12 @@
#[cfg(any(avr_mcu_atmega48p, feature = "all-mcus"))] pub mod atmega48p;
#[cfg(avr_mcu_atmega48p)] pub use self::atmega48p as current;
/// The ATmega328.
///
/// This device is chosen as the default when the crate is targeting non-AVR devices.
#[cfg(any(avr_mcu_atmega328, feature = "all-mcus", not(target_arch = "avr")))] pub mod atmega328;
#[cfg(any(avr_mcu_atmega328, not(target_arch = "avr")))] pub use self::atmega328 as current;
/// The ATmega88A.
#[cfg(any(avr_mcu_atmega88a, feature = "all-mcus"))] pub mod atmega88a;
#[cfg(avr_mcu_atmega88a)] pub use self::atmega88a as current;
/// The ATmega48.
#[cfg(any(avr_mcu_atmega48, feature = "all-mcus"))] pub mod atmega48;
#[cfg(avr_mcu_atmega48)] pub use self::atmega48 as current;
/// The ATmega168.
#[cfg(any(avr_mcu_atmega168, feature = "all-mcus"))] pub mod atmega168;
#[cfg(avr_mcu_atmega168)] pub use self::atmega168 as current;

31
src/modules/spi/mod.rs
View File

@ -1,34 +1,34 @@
mod clock;
// FIXME: Start using this module or delete!!!
#[allow(dead_code)] mod settings;
#[allow(dead_code)]
mod settings;
use crate::{Register, Pin};
use crate::{Pin, Register};
/// An SPI module.
///
/// Information at [maxembedded.com](http://maxembedded.com/2013/11/the-spi-of-the-avr/).
pub trait HardwareSpi {
type MasterInSlaveOut: Pin;
type MasterOutSlaveIn: Pin;
type SerialDataIn: Pin;
type SerialDataOu: Pin;
type Clock: Pin;
type SlaveSelect: Pin;
type ChipSelect: Pin;
/// The SPI control register.
type ControlRegister: Register<T=u8>;
type ControlRegister: Register<T = u8>;
/// The SPI status register.
type StatusRegister: Register<T=u8>;
type StatusRegister: Register<T = u8>;
/// The SPI data register.
type DataRegister: Register<T=u8>;
type DataRegister: Register<T = u8>;
/// Sets up the SPI as a master.
fn setup_master(clock: u32) {
// Setup DDR registers.
Self::MasterInSlaveOut::set_input();
Self::MasterOutSlaveIn::set_output();
Self::SerialDataIn::set_input();
Self::SerialDataOut::set_output();
Self::Clock::set_output();
Self::SlaveSelect::set_input();
Self::ChipSelect::set_input();
Self::set_master();
Self::enable_interrupt();
@ -38,10 +38,10 @@ pub trait HardwareSpi {
/// Sets up the SPI as a slave.
fn setup_slave(clock: u32) {
// Setup DDR registers.
Self::MasterInSlaveOut::set_output();
Self::MasterOutSlaveIn::set_input();
Self::SerialDataIn::set_output();
Self::SerialDataOut::set_input();
Self::Clock::set_input();
Self::SlaveSelect::set_input();
Self::ChipSelect::set_input();
Self::set_slave();
Self::setup_common(clock)
@ -147,4 +147,3 @@ pub trait HardwareSpi {
Self::DataRegister::read()
}
}