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Place ports into their own module

This commit is contained in:
Dylan McKay 2017-08-31 02:20:28 +12:00
parent 61b32145df
commit fcca0f8c27
2 changed files with 30 additions and 20 deletions
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32
build.rs
View File

@ -53,7 +53,7 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
writeln!(w, "//! Core for {}.", mcu.device.name)?; writeln!(w, "//! Core for {}.", mcu.device.name)?;
writeln!(w)?; writeln!(w)?;
writeln!(w, "use {{HardwareSpi, HardwareUsart, Pin, Register}};")?; writeln!(w, "use {{HardwareSpi, HardwareUsart, Register}};")?;
writeln!(w)?; writeln!(w)?;
gen::write_registers(mcu, w)?; gen::write_registers(mcu, w)?;
@ -87,10 +87,17 @@ mod gen {
pub fn write_pins(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { pub fn write_pins(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
if let Some(port) = mcu.peripheral("PORT") { if let Some(port) = mcu.peripheral("PORT") {
writeln!(w, "pub mod port {{")?;
writeln!(w, " use super::*;")?;
writeln!(w, " use Pin;")?;
writeln!(w)?;
for instance in port.instances.iter() { for instance in port.instances.iter() {
let port_letter = instance.name.chars().rev().next().unwrap();
for signal in instance.signals.iter() { for signal in instance.signals.iter() {
let idx = signal.index.expect("signal with no index"); let idx = signal.index.expect("signal with no index");
let struct_name = pin_name(instance, signal); let struct_name = format!("{}{}", port_letter, idx);
let io_module = mcu.modules.iter().find(|m| m.name == "PORT") let io_module = mcu.modules.iter().find(|m| m.name == "PORT")
.expect("no port io module defined for this port"); .expect("no port io module defined for this port");
@ -98,9 +105,9 @@ mod gen {
.find(|rg| rg.name == instance.name) .find(|rg| rg.name == instance.name)
.expect("no register group defined for this port"); .expect("no register group defined for this port");
writeln!(w, "pub struct {};", struct_name)?; writeln!(w, " pub struct {};", struct_name)?;
writeln!(w)?; writeln!(w)?;
writeln!(w, "impl Pin for {} {{", struct_name)?; writeln!(w, " impl Pin for {} {{", struct_name)?;
for reg in register_group.registers.iter() { for reg in register_group.registers.iter() {
let mut const_name = reg.name.clone(); let mut const_name = reg.name.clone();
const_name.pop(); // Pop port character from register name (DDRB/PORTB/etc).. const_name.pop(); // Pop port character from register name (DDRB/PORTB/etc)..
@ -110,10 +117,13 @@ mod gen {
} }
writeln!(w, " /// {}", signal.pad)?; writeln!(w, " /// {}", signal.pad)?;
writeln!(w, " const MASK: u8 = 1<<{};", idx)?; writeln!(w, " const MASK: u8 = 1<<{};", idx)?;
writeln!(w, "}}")?; writeln!(w, " }}")?;
writeln!(w)?; writeln!(w)?;
} }
} }
writeln!(w, "}}")?;
writeln!(w)?;
} }
Ok(()) Ok(())
} }
@ -152,11 +162,10 @@ mod gen {
_ => panic!("unknown SPI module register: {}", reg.caption), _ => panic!("unknown SPI module register: {}", reg.caption),
}; };
writeln!(w, " /// {}.", reg.caption)?;
writeln!(w, " type {} = {};", const_name, reg.name)?; writeln!(w, " type {} = {};", const_name, reg.name)?;
} }
writeln!(w, "}}")?; writeln!(w, "}}")?;
writeln!(w)?;
} }
Ok(()) Ok(())
} }
@ -170,12 +179,12 @@ mod gen {
writeln!(w, "impl HardwareUsart for {} {{", usart.name)?; writeln!(w, "impl HardwareUsart for {} {{", usart.name)?;
for register in usart.registers.iter() { for register in usart.registers.iter() {
let reg_ty = if register.name.starts_with("UDR") { // the data register. let reg_ty = if register.name.starts_with("UDR") { // the data register.
"UDR".to_owned() "DataRegister".to_owned()
} else if register.name.starts_with("UCSR") { // one of the three control/status registers. } else if register.name.starts_with("UCSR") { // one of the three control/status registers.
let suffix = register.name.chars().rev().next().unwrap(); let suffix = register.name.chars().rev().next().unwrap();
format!("UCSR{}", suffix) format!("ControlRegister{}", suffix)
} else if register.name.starts_with("UBRR") { // the baud rate register. } else if register.name.starts_with("UBRR") { // the baud rate register.
"UBRR".to_owned() "BaudRateRegister".to_owned()
} else { } else {
panic!("unknown usart register '{}'", register.name); panic!("unknown usart register '{}'", register.name);
}; };
@ -191,7 +200,8 @@ mod gen {
/// Gets the name of a pin. /// Gets the name of a pin.
fn pin_name(instance: &Instance, signal: &Signal) -> String { fn pin_name(instance: &Instance, signal: &Signal) -> String {
let idx = signal.index.expect("signal with no index"); let idx = signal.index.expect("signal with no index");
format!("{}{}", instance.name, idx) let letter = instance.name.chars().rev().next().unwrap();
format!("port::{}{}", letter, idx)
} }
} }

10
src/usart.rs
View File

@ -2,13 +2,13 @@ use Register;
pub trait HardwareUsart { pub trait HardwareUsart {
/// The USART data register. /// The USART data register.
type UDR: Register<u8>; type DataRegister: Register<u8>;
/// USART control and status register A. /// USART control and status register A.
type UCSRA: Register<u8>; type ControlRegisterA: Register<u8>;
/// USART control and status register B. /// USART control and status register B.
type UCSRB: Register<u8>; type ControlRegisterB: Register<u8>;
/// USART control and status register C. /// USART control and status register C.
type UCSRC: Register<u8>; type ControlRegisterC: Register<u8>;
/// USART baud rate register. /// USART baud rate register.
type UBRR: Register<u16>; type BaudRateRegister: Register<u16>;
} }