325 lines
14 KiB
Rust
325 lines
14 KiB
Rust
extern crate avr_mcu;
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use avr_mcu::*;
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use std::fs::{self, File};
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use std::io;
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use std::io::prelude::*;
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use std::path::{Path, PathBuf};
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fn src_path() -> PathBuf {
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Path::new(env!("CARGO_MANIFEST_DIR")).join("src")
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}
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fn cores_path() -> PathBuf {
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src_path().join("cores")
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}
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fn core_module_name(mcu: &Mcu) -> String {
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mcu.device.name.to_lowercase().to_owned()
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}
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fn main() {
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if !cores_path().exists() {
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fs::create_dir_all(&cores_path()).expect("could not create cores directory");
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}
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let current_mcu = avr_mcu::current::mcu()
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.expect("no target cpu specified");
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generate_config_module().unwrap();
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generate_cores(&[current_mcu]).unwrap();
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}
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fn generate_cores(mcus: &[Mcu]) -> Result<(), io::Error> {
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for mcu in mcus {
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generate_core_module(mcu).expect("failed to generate mcu core");
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}
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generate_cores_mod_rs(mcus)
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}
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fn generate_config_module() -> Result<(), io::Error> {
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let path = src_path().join("config.rs");
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let mut f = File::create(&path)?;
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let clock = env!("AVR_CPU_FREQUENCY");
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writeln!(f, "pub const CPU_FREQUENCY: u32 = {};", clock)?;
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Ok(())
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}
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fn generate_core_module(mcu: &Mcu) -> Result<(), io::Error> {
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let path = cores_path().join(format!("{}.rs", core_module_name(mcu)));
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let mut file = File::create(&path)?;
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write_core_module(mcu, &mut file)
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}
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fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
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let path = cores_path().join("mod.rs");
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let mut w = File::create(&path)?;
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writeln!(w, "//! Cores")?;
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writeln!(w)?;
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for mcu in mcus {
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let module_name = core_module_name(mcu);
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writeln!(w, "/// The {}.", mcu.device.name)?;
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writeln!(w, "pub mod {};", module_name)?;
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writeln!(w, "#[cfg(all(target_arch = \"avr\", target_cpu = \"{}\"))]", module_name)?;
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writeln!(w, "pub use self::{} as current;", module_name)?;
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}
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writeln!(w)
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}
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fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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writeln!(w, "//! Core for {}.", mcu.device.name)?;
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writeln!(w)?;
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writeln!(w, "use {{Mask, Bitset, Register}};")?;
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writeln!(w, "use modules;")?;
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writeln!(w)?;
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gen::write_registers(mcu, w)?;
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gen::write_pins(mcu, w)?;
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gen::write_spi_modules(mcu, w)?;
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gen::write_usarts(mcu, w)?;
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gen::write_timers(mcu, w)?;
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writeln!(w)
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}
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mod gen {
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use avr_mcu::*;
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use std::io;
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use std::io::prelude::*;
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pub fn write_registers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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for register in mcu.registers() {
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let ty = if register.size == 1 { "u8" } else { "u16" };
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// HACK: Skip, atmeg328p pack defines two of these.
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if register.name == "GTCCR" { continue; }
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writeln!(w, "pub struct {};", register.name)?;
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writeln!(w)?;
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writeln!(w, "impl {} {{", register.name)?;
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for bitfield in register.bitfields.iter() {
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// Create a mask for the whole bitset.
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writeln!(w, " pub const {}: Bitset<{}, Self> = Bitset::new(0x{:x});", bitfield.name, ty, bitfield.mask)?;
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// We create masks for the individual bits in the field if there
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// is more than one bit in the field.
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let mut current_mask = bitfield.mask;
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let mut current_mask_bit_num = 0;
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for current_register_bit_num in 0..15 {
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if (current_mask & 0b1) == 0b1 {
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writeln!(w, " pub const {}{}: Mask<{}, Self> = Mask::new(1<<{});",
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bitfield.name, current_mask_bit_num, ty, current_register_bit_num)?;
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current_mask_bit_num += 1;
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}
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current_mask >>= 1;
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}
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writeln!(w)?;
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}
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writeln!(w, "}}")?;
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writeln!(w)?;
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writeln!(w, "impl Register<{}> for {} {{", ty, register.name)?;
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writeln!(w, " const ADDR: *mut {} = 0x{:x} as *mut {};", ty, register.offset, ty)?;
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writeln!(w, "}}")?;
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}
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Ok(())
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}
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pub fn write_pins(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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if let Some(port) = mcu.peripheral("PORT") {
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writeln!(w, "pub mod port {{")?;
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writeln!(w, " use super::*;")?;
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writeln!(w, " use Pin;")?;
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writeln!(w)?;
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for instance in port.instances.iter() {
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let port_letter = instance.name.chars().rev().next().unwrap();
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for signal in instance.signals.iter() {
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let idx = signal.index.expect("signal with no index");
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let struct_name = format!("{}{}", port_letter, idx);
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let io_module = mcu.modules.iter().find(|m| m.name == "PORT")
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.expect("no port io module defined for this port");
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let register_group = io_module.register_groups.iter()
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.find(|rg| rg.name == instance.name)
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.expect("no register group defined for this port");
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writeln!(w, " pub struct {};", struct_name)?;
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writeln!(w)?;
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writeln!(w, " impl Pin for {} {{", struct_name)?;
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for reg in register_group.registers.iter() {
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let mut const_name = reg.name.clone();
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const_name.pop(); // Pop port character from register name (DDRB/PORTB/etc)..
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writeln!(w, " /// {}.", reg.caption)?;
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writeln!(w, " type {} = {};", const_name, reg.name)?;
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}
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writeln!(w, " /// {}", signal.pad)?;
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writeln!(w, " const MASK: u8 = 1<<{};", idx)?;
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writeln!(w, " }}")?;
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writeln!(w)?;
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}
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}
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writeln!(w, "}}")?;
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writeln!(w)?;
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}
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Ok(())
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}
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pub fn write_spi_modules(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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if let Some(module) = mcu.module("SPI") {
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let peripheral = mcu.peripheral("SPI").expect("found SPI module but no peripheral");
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let port_peripheral = mcu.port_peripheral();
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writeln!(w, "pub struct Spi;")?;
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writeln!(w)?;
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writeln!(w, "impl modules::HardwareSpi for Spi {{")?;
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for spi_signal in peripheral.signals() {
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let spi_signal_name = spi_signal.group.clone().expect("spi signal does not have group name");
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let (port_instance, port_signal) = port_peripheral.instance_signal_with_pad(&spi_signal.pad)
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.expect("no port signal associated with the spi signal pad");
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let pin_name = self::pin_name(port_instance, port_signal);
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let const_name = match &spi_signal_name[..] {
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"MISO" => "MasterInSlaveOut",
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"MOSI" => "MasterOutSlaveIn",
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"SCK" => "Clock",
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"SS" => "SlaveSelect",
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_ => panic!("unknown spi signal name: '{}'", spi_signal_name),
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};
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writeln!(w, " type {} = {};", const_name, pin_name)?;
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}
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for reg in module.registers() {
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let const_name = match ®.caption[..] {
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"SPI Data Register" => "DataRegister",
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"SPI Status Register" => "StatusRegister",
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"SPI Control Register" => "ControlRegister",
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_ => panic!("unknown SPI module register: {}", reg.caption),
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};
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writeln!(w, " type {} = {};", const_name, reg.name)?;
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}
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writeln!(w, "}}")?;
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writeln!(w)?;
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}
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Ok(())
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}
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pub fn write_usarts(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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if let Some(module) = mcu.module("USART") {
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for usart in module.register_groups.iter() {
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writeln!(w, "/// The {} module.", usart.name)?;
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writeln!(w, "pub struct {};", usart.name)?;
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writeln!(w)?;
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writeln!(w, "impl modules::HardwareUsart for {} {{", usart.name)?;
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for register in usart.registers.iter() {
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let reg_ty = if register.name.starts_with("UDR") { // the data register.
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"DataRegister".to_owned()
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} else if register.name.starts_with("UCSR") { // one of the three control/status registers.
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let suffix = register.name.chars().rev().next().unwrap();
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format!("ControlRegister{}", suffix)
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} else if register.name.starts_with("UBRR") { // the baud rate register.
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"BaudRateRegister".to_owned()
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} else {
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panic!("unknown usart register '{}'", register.name);
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};
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writeln!(w, " type {} = {};", reg_ty, register.name)?;
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}
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writeln!(w, "}}")?;
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writeln!(w)?;
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}
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}
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Ok(())
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}
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pub fn write_timers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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if let Some(tc) = mcu.module("TC8") { // Timer/Counter, 8-bit.
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const TYPE_NAME: &'static str = "Timer8";
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let find_reg = |name: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name))
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.expect(&format!("could not find '{}' register", name))
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};
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let find_reg_suffix = |name: &'static str, suffix: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
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.expect(&format!("could not find '{}' register", name))
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};
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writeln!(w, "/// 8-bit timer.")?;
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writeln!(w, "pub struct {};", TYPE_NAME)?;
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writeln!(w)?;
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writeln!(w, "impl modules::Timer8 for {} {{", TYPE_NAME)?;
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writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
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writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
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writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
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writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
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writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
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writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
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writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
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writeln!(w, " const CS0: Mask<u8, Self::ControlB> = Self::ControlB::CS00;")?;
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writeln!(w, " const CS1: Mask<u8, Self::ControlB> = Self::ControlB::CS01;")?;
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writeln!(w, " const CS2: Mask<u8, Self::ControlB> = Self::ControlB::CS02;")?;
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writeln!(w, " const WGM0: Mask<u8, Self::ControlA> = Self::ControlA::WGM00;")?;
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writeln!(w, " const WGM1: Mask<u8, Self::ControlA> = Self::ControlA::WGM01;")?;
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writeln!(w, " const WGM2: Mask<u8, Self::ControlB> = Self::ControlB::WGM020;")?;
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writeln!(w, " const OCIEA: Bitset<u8, Self::InterruptMask> = Self::InterruptMask::OCIE0A;")?;
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writeln!(w, "}}")?;
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}
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if let Some(tc) = mcu.module("TC16") { // Timer/Counter, 16-bit.
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const TYPE_NAME: &'static str = "Timer16";
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let find_reg = |name: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name))
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.expect(&format!("could not find '{}' register", name))
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};
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let find_reg_suffix = |name: &'static str, suffix: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
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.expect(&format!("could not find '{}' register", name))
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};
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writeln!(w, "/// 16-bit timer.")?;
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writeln!(w, "pub struct {};", TYPE_NAME)?;
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writeln!(w)?;
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writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?;
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writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
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writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
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writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
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writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
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writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
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writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?;
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writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
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writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
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writeln!(w, " const CS0: Mask<u8, Self::ControlB> = Self::ControlB::CS10;")?;
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writeln!(w, " const CS1: Mask<u8, Self::ControlB> = Self::ControlB::CS11;")?;
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writeln!(w, " const CS2: Mask<u8, Self::ControlB> = Self::ControlB::CS12;")?;
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writeln!(w, " const WGM0: Mask<u8, Self::ControlA> = Self::ControlA::WGM10;")?;
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writeln!(w, " const WGM1: Mask<u8, Self::ControlA> = Self::ControlA::WGM11;")?;
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writeln!(w, " const WGM2: Mask<u8, Self::ControlB> = Self::ControlB::WGM10;")?;
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writeln!(w, " const WGM3: Mask<u8, Self::ControlB> = Self::ControlB::WGM11;")?;
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writeln!(w, " const OCIEA: Bitset<u8, Self::InterruptMask> = Self::InterruptMask::OCIE1A;")?;
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writeln!(w, "}}")?;
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}
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Ok(())
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}
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/// Gets the name of a pin.
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fn pin_name(instance: &Instance, signal: &Signal) -> String {
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let idx = signal.index.expect("signal with no index");
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let letter = instance.name.chars().rev().next().unwrap();
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format!("port::{}{}", letter, idx)
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}
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}
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