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Rename RegVal to Register

This commit is contained in:
Dylan McKay 2017-09-23 16:50:01 +12:00
parent a19ef84d8d
commit 72b0169d53
3 changed files with 6 additions and 8 deletions
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4
src/lib.rs
View File

@ -8,7 +8,7 @@
#![no_std] #![no_std]
pub use self::reg::Register; pub use self::register::{Register, RegisterValue};
pub use self::pin::Pin; pub use self::pin::Pin;
pub use self::usart::HardwareUsart; pub use self::usart::HardwareUsart;
@ -20,7 +20,7 @@ pub mod cores;
pub mod spi; pub mod spi;
mod reg; mod register;
mod pin; mod pin;
mod usart; mod usart;

8
src/reg.rs → src/register.rs
View File

@ -1,6 +1,6 @@
use core::{cmp, convert, ops}; use core::{cmp, convert, ops};
pub trait RegVal : Copy + Clone + pub trait RegisterValue : Copy + Clone +
ops::BitAnd<Output=Self> + ops::BitAnd<Output=Self> +
ops::BitAndAssign + ops::BitAndAssign +
ops::BitOr<Output=Self> + ops::BitOr<Output=Self> +
@ -14,7 +14,7 @@ pub trait RegVal : Copy + Clone +
} }
/// A register. /// A register.
pub trait Register<T: RegVal> { pub trait Register<T: RegisterValue> {
/// The address of the register. /// The address of the register.
const ADDR: *mut T; const ADDR: *mut T;
@ -90,6 +90,6 @@ pub trait Register<T: RegVal> {
} }
} }
impl RegVal for u8 { } impl RegisterValue for u8 { }
impl RegVal for u16 { } impl RegisterValue for u16 { }

2
src/spi.rs
View File

@ -1,6 +1,5 @@
use {Register, Pin}; use {Register, Pin};
/// An SPI module. /// An SPI module.
/// ///
/// Information at /// Information at
@ -149,7 +148,6 @@ pub mod control_register {
} }
/// Constants for the status register. /// Constants for the status register.
#[allow(dead_code)]
pub mod status_register { pub mod status_register {
/// SPI interrupt flag. /// SPI interrupt flag.
pub const SPIF: u8 = 1<<7; pub const SPIF: u8 = 1<<7;