parent
f90d5b2d0b
commit
aecd4edb36
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@ -52,6 +52,7 @@ fn generate_config_module() -> Result<(), io::Error> {
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let mut f = File::create(&path)?;
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let clock = env!("AVR_CPU_FREQUENCY_HZ");
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writeln!(f, "/// The clock frequency of device being targeted in Hertz.")?;
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writeln!(f, "pub const CPU_FREQUENCY_HZ: u32 = {};", clock)?;
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Ok(())
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}
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@ -81,7 +82,7 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
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fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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writeln!(w, "//! Core for {}.", mcu.device.name)?;
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writeln!(w)?;
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writeln!(w, "use {{Mask, Register}};")?;
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writeln!(w, "use {{RegisterBits, Register}};")?;
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writeln!(w, "use modules;")?;
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writeln!(w)?;
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@ -15,7 +15,7 @@ pub fn write_registers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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writeln!(w, "impl {} {{", register.name)?;
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for bitfield in register.bitfields.iter() {
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// Create a mask for the whole bitset.
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writeln!(w, " pub const {}: Mask<Self> = Mask::new(0x{:x});", bitfield.name, bitfield.mask)?;
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writeln!(w, " pub const {}: RegisterBits<Self> = RegisterBits::new(0x{:x});", bitfield.name, bitfield.mask)?;
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// We create masks for the individual bits in the field if there
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// is more than one bit in the field.
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@ -23,7 +23,7 @@ pub fn write_registers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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let mut current_mask_bit_num = 0;
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for current_register_bit_num in 0..15 {
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if (current_mask & 0b1) == 0b1 {
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writeln!(w, " pub const {}{}: Mask<Self> = Mask::new(1<<{});",
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writeln!(w, " pub const {}{}: RegisterBits<Self> = RegisterBits::new(1<<{});",
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bitfield.name, current_mask_bit_num, current_register_bit_num)?;
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current_mask_bit_num += 1;
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}
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@ -182,13 +182,13 @@ pub fn write_timers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
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writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
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writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
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writeln!(w, " const CS0: Mask<Self::ControlB> = Self::ControlB::CS00;")?;
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writeln!(w, " const CS1: Mask<Self::ControlB> = Self::ControlB::CS01;")?;
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writeln!(w, " const CS2: Mask<Self::ControlB> = Self::ControlB::CS02;")?;
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writeln!(w, " const WGM0: Mask<Self::ControlA> = Self::ControlA::WGM00;")?;
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writeln!(w, " const WGM1: Mask<Self::ControlA> = Self::ControlA::WGM01;")?;
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writeln!(w, " const WGM2: Mask<Self::ControlB> = Self::ControlB::WGM020;")?;
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writeln!(w, " const OCIEA: Mask<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
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writeln!(w, " const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS00;")?;
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writeln!(w, " const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS01;")?;
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writeln!(w, " const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS02;")?;
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writeln!(w, " const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM00;")?;
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writeln!(w, " const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM01;")?;
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writeln!(w, " const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM020;")?;
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writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
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writeln!(w, "}}")?;
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}
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@ -218,14 +218,14 @@ pub fn write_timers(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?;
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writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
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writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
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writeln!(w, " const CS0: Mask<Self::ControlB> = Self::ControlB::CS10;")?;
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writeln!(w, " const CS1: Mask<Self::ControlB> = Self::ControlB::CS11;")?;
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writeln!(w, " const CS2: Mask<Self::ControlB> = Self::ControlB::CS12;")?;
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writeln!(w, " const WGM0: Mask<Self::ControlA> = Self::ControlA::WGM10;")?;
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writeln!(w, " const WGM1: Mask<Self::ControlA> = Self::ControlA::WGM11;")?;
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writeln!(w, " const WGM2: Mask<Self::ControlB> = Self::ControlB::WGM10;")?;
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writeln!(w, " const WGM3: Mask<Self::ControlB> = Self::ControlB::WGM11;")?;
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writeln!(w, " const OCIEA: Mask<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
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writeln!(w, " const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS10;")?;
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writeln!(w, " const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS11;")?;
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writeln!(w, " const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS12;")?;
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writeln!(w, " const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM10;")?;
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writeln!(w, " const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM11;")?;
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writeln!(w, " const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM10;")?;
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writeln!(w, " const WGM3: RegisterBits<Self::ControlB> = Self::ControlB::WGM11;")?;
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writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
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writeln!(w, "}}")?;
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}
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@ -14,7 +14,7 @@
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#![no_std]
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pub use self::register::{Mask, Register, RegisterValue};
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pub use self::register::{Register, RegisterBits, RegisterValue};
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pub use self::pin::{DataDirection, Pin};
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pub mod prelude;
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@ -56,87 +56,87 @@ pub trait HardwareSpi {
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/// Sets the clock speed.
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fn set_clock(clock: u32) {
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let mask = clock::ClockMask::with_clock(clock);
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Self::ControlRegister::set_raw(mask.control_register_mask());
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Self::StatusRegister::set_raw(mask.status_register_mask());
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Self::ControlRegister::set_mask_raw(mask.control_register_mask());
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Self::StatusRegister::set_mask_raw(mask.status_register_mask());
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}
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/// Enables interrupts for the spi module.
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#[inline(always)]
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fn enable_interrupt() {
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Self::ControlRegister::set_raw(settings::control_register::INTERRUPT_ENABLE);
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Self::ControlRegister::set_mask_raw(settings::control_register::INTERRUPT_ENABLE);
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}
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/// Disables interrupts for the spi module.
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#[inline(always)]
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fn disable_interrupt() {
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Self::ControlRegister::unset_raw(settings::control_register::INTERRUPT_ENABLE);
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Self::ControlRegister::unset_mask_raw(settings::control_register::INTERRUPT_ENABLE);
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}
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/// Enables the SPI.
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#[inline(always)]
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fn enable() {
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Self::ControlRegister::set_raw(settings::control_register::ENABLE);
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Self::ControlRegister::set_mask_raw(settings::control_register::ENABLE);
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}
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/// Disables the SPI.
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#[inline(always)]
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fn disable() {
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Self::ControlRegister::unset_raw(settings::control_register::ENABLE);
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Self::ControlRegister::unset_mask_raw(settings::control_register::ENABLE);
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}
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/// Enables least-significant-bit first.
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#[inline(always)]
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fn set_lsb() {
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Self::ControlRegister::set_raw(settings::control_register::DATA_ORDER_LSB);
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Self::ControlRegister::set_mask_raw(settings::control_register::DATA_ORDER_LSB);
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}
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/// Enables most-significant-bit first.
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#[inline(always)]
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fn set_msb() {
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Self::ControlRegister::unset_raw(settings::control_register::DATA_ORDER_LSB);
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Self::ControlRegister::unset_mask_raw(settings::control_register::DATA_ORDER_LSB);
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}
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/// Enables master mode.
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#[inline(always)]
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fn set_master() {
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Self::ControlRegister::set_raw(settings::control_register::MASTER);
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Self::ControlRegister::set_mask_raw(settings::control_register::MASTER);
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}
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/// Enables slave mode.
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#[inline(always)]
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fn set_slave() {
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Self::ControlRegister::unset_raw(settings::control_register::MASTER);
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Self::ControlRegister::unset_mask_raw(settings::control_register::MASTER);
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}
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/// Enables double speed mode.
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#[inline(always)]
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fn enable_double_speed() {
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Self::StatusRegister::set_raw(settings::status_register::SPI2X);
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Self::StatusRegister::set_mask_raw(settings::status_register::SPI2X);
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}
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/// Disables double speed mode.
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#[inline(always)]
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fn disable_double_speed() {
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Self::StatusRegister::unset_raw(settings::status_register::SPI2X);
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Self::StatusRegister::unset_mask_raw(settings::status_register::SPI2X);
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}
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/// Checks if there is a write collision.
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#[inline(always)]
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fn is_write_collision() -> bool {
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Self::StatusRegister::is_set_raw(settings::status_register::WCOL)
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Self::StatusRegister::is_mask_set_raw(settings::status_register::WCOL)
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}
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/// Sends a byte through the serial.
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#[inline(always)]
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fn send_byte(byte: u8) {
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Self::DataRegister::write(byte);
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Self::StatusRegister::wait_until_set_raw(settings::status_register::SPIF);
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Self::StatusRegister::wait_until_mask_set_raw(settings::status_register::SPIF);
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}
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/// Reads a byte from the serial.
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#[inline(always)]
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fn receive_byte() -> u8 {
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Self::StatusRegister::wait_until_set_raw(settings::status_register::SPIF);
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Self::StatusRegister::wait_until_mask_set_raw(settings::status_register::SPIF);
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Self::DataRegister::read()
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}
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@ -144,7 +144,7 @@ pub trait HardwareSpi {
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#[inline(always)]
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fn send_receive(byte: u8) -> u8 {
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Self::DataRegister::write(byte);
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Self::StatusRegister::wait_until_set_raw(settings::status_register::SPIF);
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Self::StatusRegister::wait_until_mask_set_raw(settings::status_register::SPIF);
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Self::DataRegister::read()
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}
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}
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@ -1,4 +1,4 @@
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use {Mask, Register};
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use {RegisterBits, Register};
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use core::marker;
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/// A 16-bit timer.
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@ -41,16 +41,16 @@ pub trait Timer16 : Sized {
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/// For example, TIFR0.
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type InterruptFlag: Register<T=u8>;
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const CS0: Mask<Self::ControlB>;
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const CS1: Mask<Self::ControlB>;
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const CS2: Mask<Self::ControlB>;
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const CS0: RegisterBits<Self::ControlB>;
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const CS1: RegisterBits<Self::ControlB>;
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const CS2: RegisterBits<Self::ControlB>;
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const WGM0: Mask<Self::ControlA>;
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const WGM1: Mask<Self::ControlA>;
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const WGM2: Mask<Self::ControlB>;
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const WGM3: Mask<Self::ControlB>;
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const WGM0: RegisterBits<Self::ControlA>;
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const WGM1: RegisterBits<Self::ControlA>;
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const WGM2: RegisterBits<Self::ControlB>;
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const WGM3: RegisterBits<Self::ControlB>;
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const OCIEA: Mask<Self::InterruptMask>;
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const OCIEA: RegisterBits<Self::InterruptMask>;
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fn setup() -> Timer16Setup<Self> { Timer16Setup::new() }
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}
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@ -67,23 +67,23 @@ pub enum ClockSource {
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}
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impl ClockSource {
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fn bits<T: Timer16>(&self) -> Mask<T::ControlB> {
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fn bits<T: Timer16>(&self) -> RegisterBits<T::ControlB> {
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use self::ClockSource::*;
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match *self {
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None => Mask::zero() | Mask::zero() | Mask::zero(),
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Prescale1 => Mask::zero() | Mask::zero() | T::CS0,
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Prescale8 => Mask::zero() | T::CS1 | Mask::zero(),
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Prescale64 => Mask::zero() | T::CS1 | T::CS0,
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Prescale256 => T::CS2 | Mask::zero() | Mask::zero(),
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Prescale1024 => T::CS2 | Mask::zero() | T::CS0,
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ExternalFalling => T::CS2 | T::CS1 | Mask::zero(),
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None => RegisterBits::zero() | RegisterBits::zero() | RegisterBits::zero(),
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Prescale1 => RegisterBits::zero() | RegisterBits::zero() | T::CS0,
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Prescale8 => RegisterBits::zero() | T::CS1 | RegisterBits::zero(),
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Prescale64 => RegisterBits::zero() | T::CS1 | T::CS0,
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Prescale256 => T::CS2 | RegisterBits::zero() | RegisterBits::zero(),
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Prescale1024 => T::CS2 | RegisterBits::zero() | T::CS0,
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ExternalFalling => T::CS2 | T::CS1 | RegisterBits::zero(),
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ExternalRising => T::CS2 | T::CS1 | T::CS0,
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}
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}
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#[inline]
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fn mask<T: Timer16>() -> Mask<T::ControlB> {
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fn mask<T: Timer16>() -> RegisterBits<T::ControlB> {
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!(T::CS2 | T::CS1 | T::CS0)
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}
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}
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@ -109,29 +109,30 @@ pub enum WaveformGenerationMode {
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impl WaveformGenerationMode {
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/// Returns bits for TCCR1A, TCCR1B
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#[inline]
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fn bits<T: Timer16>(&self) -> (Mask<T::ControlA>, Mask<T::ControlB>) {
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fn bits<T: Timer16>(&self) -> (RegisterBits<T::ControlA>, RegisterBits<T::ControlB>) {
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use self::WaveformGenerationMode::*;
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use RegisterBits as B;
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// It makes more sense to return bytes (A,B), but the manual
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// lists the table as (B,A). We match the manual here for
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// inspection purposes and flip the values for sanity
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// purposes.
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let (b, a) = match *self {
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Normal => (Mask::zero() | Mask::zero(), Mask::zero() | Mask::zero()),
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PwmPhaseCorrect8Bit => (Mask::zero() | Mask::zero(), Mask::zero() | T::WGM0),
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PwmPhaseCorrect9Bit => (Mask::zero() | Mask::zero(), T::WGM1 | Mask::zero()),
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PwmPhaseCorrect10Bit => (Mask::zero() | Mask::zero(), T::WGM1 | T::WGM0),
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ClearOnTimerMatchOutputCompare => (Mask::zero() | T::WGM2, Mask::zero() | Mask::zero()),
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FastPwm8Bit => (Mask::zero() | T::WGM2, Mask::zero() | T::WGM0),
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FastPwm9Bit => (Mask::zero() | T::WGM2, T::WGM1 | Mask::zero()),
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FastPwm10Bit => (Mask::zero() | T::WGM2, T::WGM1 | T::WGM0),
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PwmPhaseAndFrequencyCorrectInputCapture => (T::WGM3 | Mask::zero(), Mask::zero() | Mask::zero()),
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PwmPhaseAndFrequencyCorrectOutputCompare => (T::WGM3 | Mask::zero(), Mask::zero() | T::WGM0),
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PwmPhaseCorrectInputCapture => (T::WGM3 | Mask::zero(), T::WGM1 | Mask::zero()),
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PwmPhaseCorrectOutputCompare => (T::WGM3 | Mask::zero(), T::WGM1 | T::WGM0),
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ClearOnTimerMatchInputCapture => (T::WGM3 | T::WGM2, Mask::zero() | Mask::zero()),
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// Reserved => (T::WGM3 | T::WGM2, Mask::zero() | T::WGM0),
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FastPwmInputCapture => (T::WGM3 | T::WGM2, T::WGM1 | Mask::zero()),
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Normal => (B::zero() | B::zero(), B::zero() | B::zero()),
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PwmPhaseCorrect8Bit => (B::zero() | B::zero(), B::zero() | T::WGM0),
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PwmPhaseCorrect9Bit => (B::zero() | B::zero(), T::WGM1 | B::zero()),
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PwmPhaseCorrect10Bit => (B::zero() | B::zero(), T::WGM1 | T::WGM0),
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ClearOnTimerMatchOutputCompare => (B::zero() | T::WGM2, B::zero() | B::zero()),
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FastPwm8Bit => (B::zero() | T::WGM2, B::zero() | T::WGM0),
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FastPwm9Bit => (B::zero() | T::WGM2, T::WGM1 | B::zero()),
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FastPwm10Bit => (B::zero() | T::WGM2, T::WGM1 | T::WGM0),
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PwmPhaseAndFrequencyCorrectInputCapture => (T::WGM3 | B::zero(), B::zero() | B::zero()),
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PwmPhaseAndFrequencyCorrectOutputCompare => (T::WGM3 | B::zero(), B::zero() | T::WGM0),
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PwmPhaseCorrectInputCapture => (T::WGM3 | B::zero(), T::WGM1 | B::zero()),
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PwmPhaseCorrectOutputCompare => (T::WGM3 | B::zero(), T::WGM1 | T::WGM0),
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ClearOnTimerMatchInputCapture => (T::WGM3 | T::WGM2, B::zero() | B::zero()),
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// Reserved => (T::WGM3 | T::WGM2, B::zero() | T::WGM0),
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FastPwmInputCapture => (T::WGM3 | T::WGM2, T::WGM1 | B::zero()),
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FastPwmOutputCompare => (T::WGM3 | T::WGM2, T::WGM1 | T::WGM0),
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};
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}
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#[inline]
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fn mask<T: Timer16>() -> (Mask<T::ControlA>, Mask<T::ControlB>) {
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fn mask<T: Timer16>() -> (RegisterBits<T::ControlA>, RegisterBits<T::ControlB>) {
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(!(T::WGM0 | T::WGM1), !(T::WGM2 | T::WGM3))
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}
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}
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pub struct Timer16Setup<T: Timer16> {
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a: Mask<T::ControlA>,
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b: Mask<T::ControlB>,
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c: Mask<T::ControlC>,
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a: RegisterBits<T::ControlA>,
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b: RegisterBits<T::ControlB>,
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c: RegisterBits<T::ControlC>,
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output_compare_1: Option<u16>,
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_phantom: marker::PhantomData<T>,
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}
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@ -156,9 +157,9 @@ impl<T: Timer16> Timer16Setup<T> {
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#[inline]
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fn new() -> Self {
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Timer16Setup {
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a: Mask::zero(),
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b: Mask::zero(),
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c: Mask::zero(),
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a: RegisterBits::zero(),
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b: RegisterBits::zero(),
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c: RegisterBits::zero(),
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output_compare_1: None,
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_phantom: marker::PhantomData,
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}
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@ -1,4 +1,4 @@
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use {Mask, Register};
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use {RegisterBits, Register};
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use core::marker;
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/// A 8-bit timer.
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||||
|
@ -37,21 +37,21 @@ pub trait Timer8 : Sized {
|
|||
type InterruptFlag: Register<T=u8>;
|
||||
|
||||
/// Bit 0 of the clock select mask.
|
||||
const CS0: Mask<Self::ControlB>;
|
||||
const CS0: RegisterBits<Self::ControlB>;
|
||||
/// Bit 1 of the clock select mask.
|
||||
const CS1: Mask<Self::ControlB>;
|
||||
const CS1: RegisterBits<Self::ControlB>;
|
||||
/// Bit 2 of the clock select mask.
|
||||
const CS2: Mask<Self::ControlB>;
|
||||
const CS2: RegisterBits<Self::ControlB>;
|
||||
|
||||
/// Bit 0 of the waveform generation mode mask.
|
||||
const WGM0: Mask<Self::ControlA>;
|
||||
const WGM0: RegisterBits<Self::ControlA>;
|
||||
/// Bit 1 of the waveform generation mode mask.
|
||||
const WGM1: Mask<Self::ControlA>;
|
||||
const WGM1: RegisterBits<Self::ControlA>;
|
||||
/// Bit 2 of the waveform generation mode mask.
|
||||
const WGM2: Mask<Self::ControlB>;
|
||||
const WGM2: RegisterBits<Self::ControlB>;
|
||||
|
||||
/// Output compare interrupt enable flag.
|
||||
const OCIEA: Mask<Self::InterruptMask>;
|
||||
const OCIEA: RegisterBits<Self::InterruptMask>;
|
||||
}
|
||||
|
||||
pub enum ClockSource {
|
||||
|
@ -66,23 +66,23 @@ pub enum ClockSource {
|
|||
}
|
||||
|
||||
impl ClockSource {
|
||||
fn bits<T: Timer8>(&self) -> Mask<T::ControlB> {
|
||||
fn bits<T: Timer8>(&self) -> RegisterBits<T::ControlB> {
|
||||
use self::ClockSource::*;
|
||||
|
||||
match *self {
|
||||
None => Mask::zero() | Mask::zero() | Mask::zero(),
|
||||
Prescale1 => Mask::zero() | Mask::zero() | T::CS0,
|
||||
Prescale8 => Mask::zero() | T::CS1 | Mask::zero(),
|
||||
Prescale64 => Mask::zero() | T::CS1 | T::CS0,
|
||||
Prescale256 => T::CS2 | Mask::zero() | Mask::zero(),
|
||||
Prescale1024 => T::CS2 | Mask::zero() | T::CS0,
|
||||
ExternalFalling => T::CS2 | T::CS1 | Mask::zero(),
|
||||
None => RegisterBits::zero() | RegisterBits::zero() | RegisterBits::zero(),
|
||||
Prescale1 => RegisterBits::zero() | RegisterBits::zero() | T::CS0,
|
||||
Prescale8 => RegisterBits::zero() | T::CS1 | RegisterBits::zero(),
|
||||
Prescale64 => RegisterBits::zero() | T::CS1 | T::CS0,
|
||||
Prescale256 => T::CS2 | RegisterBits::zero() | RegisterBits::zero(),
|
||||
Prescale1024 => T::CS2 | RegisterBits::zero() | T::CS0,
|
||||
ExternalFalling => T::CS2 | T::CS1 | RegisterBits::zero(),
|
||||
ExternalRising => T::CS2 | T::CS1 | T::CS0,
|
||||
}
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn mask<T: Timer8>() -> Mask<T::ControlB> {
|
||||
fn mask<T: Timer8>() -> RegisterBits<T::ControlB> {
|
||||
!(T::CS2 | T::CS1 | T::CS0)
|
||||
}
|
||||
}
|
||||
|
@ -99,7 +99,7 @@ pub enum WaveformGenerationMode {
|
|||
impl WaveformGenerationMode {
|
||||
/// Returns bits for TCCR0A, TCCR0B
|
||||
#[inline]
|
||||
fn bits<T: Timer8>(&self) -> (Mask<T::ControlA>, Mask<T::ControlB>) {
|
||||
fn bits<T: Timer8>(&self) -> (RegisterBits<T::ControlA>, RegisterBits<T::ControlB>) {
|
||||
use self::WaveformGenerationMode::*;
|
||||
|
||||
// It makes more sense to return bytes (A,B), but the manual
|
||||
|
@ -107,13 +107,13 @@ impl WaveformGenerationMode {
|
|||
// inspection purposes and flip the values for sanity
|
||||
// purposes.
|
||||
let (b, a) = match *self {
|
||||
Normal => (Mask::zero(), Mask::zero() | Mask::zero()),
|
||||
PwmPhaseCorrect => (Mask::zero(), Mask::zero() | T::WGM0),
|
||||
ClearOnTimerMatchOutputCompare => (Mask::zero(), T::WGM1 | Mask::zero()),
|
||||
FastPwm => (Mask::zero(), T::WGM1 | T::WGM0),
|
||||
// Reserved => (T::WGM2, Mask::zero() | Mask::zero()),
|
||||
PwmPhaseCorrectOutputCompare => (T::WGM2, Mask::zero() | T::WGM0),
|
||||
// Reserved => (T::WGM2, T::WGM1 | Mask::zero())),
|
||||
Normal => (RegisterBits::zero(), RegisterBits::zero() | RegisterBits::zero()),
|
||||
PwmPhaseCorrect => (RegisterBits::zero(), RegisterBits::zero() | T::WGM0),
|
||||
ClearOnTimerMatchOutputCompare => (RegisterBits::zero(), T::WGM1 | RegisterBits::zero()),
|
||||
FastPwm => (RegisterBits::zero(), T::WGM1 | T::WGM0),
|
||||
// Reserved => (T::WGM2, RegisterBits::zero() | RegisterBits::zero()),
|
||||
PwmPhaseCorrectOutputCompare => (T::WGM2, RegisterBits::zero() | T::WGM0),
|
||||
// Reserved => (T::WGM2, T::WGM1 | RegisterBits::zero())),
|
||||
FastPwmOutputCompare => (T::WGM2, T::WGM1 | T::WGM0),
|
||||
};
|
||||
|
||||
|
@ -121,14 +121,14 @@ impl WaveformGenerationMode {
|
|||
}
|
||||
|
||||
#[inline]
|
||||
fn mask<T: Timer8>() -> (Mask<T::ControlA>, Mask<T::ControlB>) {
|
||||
fn mask<T: Timer8>() -> (RegisterBits<T::ControlA>, RegisterBits<T::ControlB>) {
|
||||
(!(T::WGM0 | T::WGM1), !(T::WGM2))
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Timer8Setup<T: Timer8> {
|
||||
a: Mask<T::ControlA>,
|
||||
b: Mask<T::ControlB>,
|
||||
a: RegisterBits<T::ControlA>,
|
||||
b: RegisterBits<T::ControlB>,
|
||||
output_compare_1: Option<u8>,
|
||||
_phantom: marker::PhantomData<T>,
|
||||
}
|
||||
|
@ -137,8 +137,8 @@ impl<T: Timer8> Timer8Setup<T> {
|
|||
#[inline]
|
||||
pub fn new() -> Self {
|
||||
Timer8Setup {
|
||||
a: Mask::zero(),
|
||||
b: Mask::zero(),
|
||||
a: RegisterBits::zero(),
|
||||
b: RegisterBits::zero(),
|
||||
output_compare_1: None,
|
||||
_phantom: marker::PhantomData,
|
||||
}
|
||||
|
|
15
src/pin.rs
15
src/pin.rs
|
@ -1,7 +1,10 @@
|
|||
use Register;
|
||||
|
||||
/// Represents whether a pin is an input or an output.
|
||||
pub enum DataDirection {
|
||||
/// The pin is exclusively used for reading signals.
|
||||
Input,
|
||||
/// The pin is exclusively used for sending signals.
|
||||
Output,
|
||||
}
|
||||
|
||||
|
@ -11,7 +14,7 @@ pub trait Pin {
|
|||
type DDR: Register<T=u8>;
|
||||
/// The associated port register.
|
||||
type PORT: Register<T=u8>;
|
||||
/// The associated pin register.
|
||||
|
||||
///
|
||||
/// Reads from the register will read input bits.
|
||||
/// Writes to the register will toggle bits.
|
||||
|
@ -31,13 +34,13 @@ pub trait Pin {
|
|||
/// Sets the pin up as an input.
|
||||
#[inline(always)]
|
||||
fn set_input() {
|
||||
Self::DDR::unset_raw(Self::MASK);
|
||||
Self::DDR::unset_mask_raw(Self::MASK);
|
||||
}
|
||||
|
||||
/// Sets the pin up as an output.
|
||||
#[inline(always)]
|
||||
fn set_output() {
|
||||
Self::DDR::set_raw(Self::MASK);
|
||||
Self::DDR::set_mask_raw(Self::MASK);
|
||||
}
|
||||
|
||||
/// Set the pin to high.
|
||||
|
@ -45,7 +48,7 @@ pub trait Pin {
|
|||
/// The pin must be configured as an output.
|
||||
#[inline(always)]
|
||||
fn set_high() {
|
||||
Self::PORT::set_raw(Self::MASK);
|
||||
Self::PORT::set_mask_raw(Self::MASK);
|
||||
}
|
||||
|
||||
/// Set the pin to low.
|
||||
|
@ -53,7 +56,7 @@ pub trait Pin {
|
|||
/// The pin must be configured as an output.
|
||||
#[inline(always)]
|
||||
fn set_low() {
|
||||
Self::PORT::unset_raw(Self::MASK);
|
||||
Self::PORT::unset_mask_raw(Self::MASK);
|
||||
}
|
||||
|
||||
/// Toggles the pin.
|
||||
|
@ -72,7 +75,7 @@ pub trait Pin {
|
|||
/// The pin must be configured as an input.
|
||||
#[inline(always)]
|
||||
fn is_high() -> bool {
|
||||
Self::PIN::is_set_raw(Self::MASK)
|
||||
Self::PIN::is_mask_set_raw(Self::MASK)
|
||||
}
|
||||
|
||||
/// Checks if the pin is currently low.
|
||||
|
|
210
src/register.rs
210
src/register.rs
|
@ -1,6 +1,8 @@
|
|||
use core::{cmp, convert, marker, ops};
|
||||
|
||||
/// A value that a register can store.
|
||||
///
|
||||
/// All registers are either `u8` or `u16`.
|
||||
pub trait RegisterValue : Copy + Clone +
|
||||
ops::BitAnd<Output=Self> +
|
||||
ops::BitAndAssign +
|
||||
|
@ -16,8 +18,11 @@ pub trait RegisterValue : Copy + Clone +
|
|||
|
||||
/// A register.
|
||||
pub trait Register : Sized {
|
||||
/// The type that can represent the value of the register.
|
||||
type T: RegisterValue;
|
||||
type Mask = Mask<Self>;
|
||||
/// The type representing a set of bits that may be manipulated
|
||||
/// within the register.
|
||||
type RegisterBits = RegisterBits<Self>;
|
||||
|
||||
/// The address of the register.
|
||||
const ADDRESS: *mut Self::T;
|
||||
|
@ -36,35 +41,44 @@ pub trait Register : Sized {
|
|||
unsafe { *Self::ADDRESS }
|
||||
}
|
||||
|
||||
fn set(mask: Mask<Self>) {
|
||||
Self::set_raw(mask.mask);
|
||||
/// Sets a set of bits to `1` in the register.
|
||||
fn set(bits: RegisterBits<Self>) {
|
||||
Self::set_mask_raw(bits.mask);
|
||||
}
|
||||
|
||||
/// Sets a bitmask in a register.
|
||||
///
|
||||
/// This is equivalent to `r |= mask`.
|
||||
#[inline(always)]
|
||||
fn set_raw(mask: Self::T) {
|
||||
fn set_mask_raw(mask: Self::T) {
|
||||
unsafe {
|
||||
*Self::ADDRESS |= mask;
|
||||
}
|
||||
}
|
||||
|
||||
fn unset(mask: Mask<Self>) {
|
||||
Self::unset_raw(mask.mask);
|
||||
/// Unsets a set of bits in the register.
|
||||
///
|
||||
/// All of the bits will be set to `0`.
|
||||
fn unset(bits: RegisterBits<Self>) {
|
||||
Self::unset_mask_raw(bits.mask);
|
||||
}
|
||||
|
||||
/// Clears a bitmask from a register.
|
||||
///
|
||||
/// This is equivalent to `r &= !mask`.
|
||||
#[inline(always)]
|
||||
fn unset_raw(mask: Self::T) {
|
||||
fn unset_mask_raw(mask: Self::T) {
|
||||
unsafe {
|
||||
*Self::ADDRESS &= !mask;
|
||||
}
|
||||
}
|
||||
|
||||
fn toggle(mask: Mask<Self>) {
|
||||
/// Toggles a set of bits within the register.
|
||||
///
|
||||
/// All specified bits which were previously `0` will become
|
||||
/// `1`, and all specified bits that were previous `1` will
|
||||
/// become `0`.
|
||||
fn toggle(mask: RegisterBits<Self>) {
|
||||
Self::toggle_raw(mask.mask);
|
||||
}
|
||||
|
||||
|
@ -78,21 +92,29 @@ pub trait Register : Sized {
|
|||
}
|
||||
}
|
||||
|
||||
fn is_set(mask: Mask<Self>) -> bool {
|
||||
Self::is_set_raw(mask.mask)
|
||||
/// Checks if a set of bits are enabled.
|
||||
///
|
||||
/// All specifed bits must be set for this function
|
||||
/// to return `true`.
|
||||
fn is_set(bits: RegisterBits<Self>) -> bool {
|
||||
Self::is_mask_set_raw(bits.mask)
|
||||
}
|
||||
|
||||
/// Checks if a mask is set in the register.
|
||||
///
|
||||
/// This is equivalent to `(r & mask) == mask`.
|
||||
#[inline(always)]
|
||||
fn is_set_raw(mask: Self::T) -> bool {
|
||||
fn is_mask_set_raw(mask: Self::T) -> bool {
|
||||
unsafe {
|
||||
(*Self::ADDRESS & mask) == mask
|
||||
}
|
||||
}
|
||||
|
||||
fn is_clear(mask: Mask<Self>) -> bool {
|
||||
/// Checks if a set of bits are not set.
|
||||
///
|
||||
/// All specified bits must be `0` for this
|
||||
/// function to return `true`.
|
||||
fn is_clear(mask: RegisterBits<Self>) -> bool {
|
||||
Self::is_clear_raw(mask.mask)
|
||||
}
|
||||
|
||||
|
@ -106,6 +128,92 @@ pub trait Register : Sized {
|
|||
}
|
||||
}
|
||||
|
||||
/// Waits until a set of bits are set in the register.
|
||||
///
|
||||
/// This function will block until all bits that are set in
|
||||
/// the mask are also set in the register.
|
||||
fn wait_until_set(bits: RegisterBits<Self>) {
|
||||
Self::wait_until_mask_set_raw(bits.mask);
|
||||
}
|
||||
|
||||
/// Waits until a bit mask is set in the register.
|
||||
///
|
||||
/// This function will block until all bits that are set in
|
||||
/// the mask are also set in the register.
|
||||
#[inline(always)]
|
||||
fn wait_until_mask_set_raw(mask: Self::T) {
|
||||
wait_until(|| Self::is_mask_set_raw(mask))
|
||||
}
|
||||
}
|
||||
|
||||
/// Represents a set of bits within a specific register.
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct RegisterBits<R: Register> {
|
||||
/// The raw bitmask.
|
||||
mask: R::T,
|
||||
_phantom: marker::PhantomData<R>,
|
||||
}
|
||||
|
||||
impl<R> RegisterBits<R> where R: Register {
|
||||
/// Creates a new register mask.
|
||||
pub const fn new(mask: R::T) -> Self {
|
||||
RegisterBits { mask, _phantom: marker::PhantomData }
|
||||
}
|
||||
|
||||
pub fn zero() -> Self {
|
||||
RegisterBits::new(0u8.into())
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::BitOr for RegisterBits<R> where R: Register
|
||||
{
|
||||
type Output = Self;
|
||||
|
||||
fn bitor(self, rhs: Self) -> Self {
|
||||
RegisterBits::new(self.mask | rhs.mask)
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::BitOrAssign for RegisterBits<R> where R: Register {
|
||||
fn bitor_assign(&mut self, rhs: Self) {
|
||||
self.mask |= rhs.mask;
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::BitAnd for RegisterBits<R> where R: Register
|
||||
{
|
||||
type Output = Self;
|
||||
|
||||
fn bitand(self, rhs: Self) -> Self {
|
||||
RegisterBits::new(self.mask & rhs.mask)
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::BitAndAssign for RegisterBits<R> where R: Register {
|
||||
fn bitand_assign(&mut self, rhs: Self) {
|
||||
self.mask &= rhs.mask;
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::Not for RegisterBits<R> where R: Register {
|
||||
type Output = Self;
|
||||
|
||||
fn not(self) -> Self {
|
||||
RegisterBits::new(!self.mask)
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> Into<u8> for RegisterBits<R> where R: Register<T=u8> {
|
||||
fn into(self) -> u8 { self.mask }
|
||||
}
|
||||
|
||||
impl<R> Into<u16> for RegisterBits<R> where R: Register<T=u16> {
|
||||
fn into(self) -> u16 { self.mask }
|
||||
}
|
||||
|
||||
impl RegisterValue for u8 { }
|
||||
impl RegisterValue for u16 { }
|
||||
|
||||
/// Waits until some condition is true of the register.
|
||||
#[inline(always)]
|
||||
fn wait_until<F>(mut f: F)
|
||||
|
@ -117,81 +225,3 @@ pub trait Register : Sized {
|
|||
}
|
||||
}
|
||||
|
||||
fn wait_until_set(mask: Mask<Self>) {
|
||||
Self::wait_until_set_raw(mask.mask);
|
||||
}
|
||||
|
||||
/// Waits until a mask is set.
|
||||
#[inline(always)]
|
||||
fn wait_until_set_raw(mask: Self::T) {
|
||||
Self::wait_until(|| Self::is_set_raw(mask))
|
||||
}
|
||||
}
|
||||
|
||||
/// A register bitmask.
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct Mask<R: Register> {
|
||||
mask: R::T,
|
||||
_phantom: marker::PhantomData<R>,
|
||||
}
|
||||
|
||||
impl<R> Mask<R> where R: Register {
|
||||
/// Creates a new register mask.
|
||||
pub const fn new(mask: R::T) -> Self {
|
||||
Mask { mask, _phantom: marker::PhantomData }
|
||||
}
|
||||
|
||||
pub fn zero() -> Self {
|
||||
Mask::new(0u8.into())
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::BitOr for Mask<R> where R: Register
|
||||
{
|
||||
type Output = Self;
|
||||
|
||||
fn bitor(self, rhs: Self) -> Self {
|
||||
Mask::new(self.mask | rhs.mask)
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::BitOrAssign for Mask<R> where R: Register {
|
||||
fn bitor_assign(&mut self, rhs: Self) {
|
||||
self.mask |= rhs.mask;
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::BitAnd for Mask<R> where R: Register
|
||||
{
|
||||
type Output = Self;
|
||||
|
||||
fn bitand(self, rhs: Self) -> Self {
|
||||
Mask::new(self.mask & rhs.mask)
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::BitAndAssign for Mask<R> where R: Register {
|
||||
fn bitand_assign(&mut self, rhs: Self) {
|
||||
self.mask &= rhs.mask;
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> ops::Not for Mask<R> where R: Register {
|
||||
type Output = Self;
|
||||
|
||||
fn not(self) -> Self {
|
||||
Mask::new(!self.mask)
|
||||
}
|
||||
}
|
||||
|
||||
impl<R> Into<u8> for Mask<R> where R: Register<T=u8> {
|
||||
fn into(self) -> u8 { self.mask }
|
||||
}
|
||||
|
||||
impl<R> Into<u16> for Mask<R> where R: Register<T=u16> {
|
||||
fn into(self) -> u16 { self.mask }
|
||||
}
|
||||
|
||||
impl RegisterValue for u8 { }
|
||||
impl RegisterValue for u16 { }
|
||||
|
||||
|
|
Loading…
Reference in New Issue