Implement the Timer16 trait

This commit is contained in:
Dylan McKay 2017-12-14 01:54:47 +13:00
parent d125f69f7d
commit 0157a8553c
6 changed files with 62 additions and 31 deletions

View File

@ -71,7 +71,7 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> { fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
writeln!(w, "//! Core for {}.", mcu.device.name)?; writeln!(w, "//! Core for {}.", mcu.device.name)?;
writeln!(w)?; writeln!(w)?;
writeln!(w, "use {{Mask, Bitset, HardwareUsart, Register}};")?; writeln!(w, "use {{Mask, Bitset, Register}};")?;
writeln!(w, "use modules;")?; writeln!(w, "use modules;")?;
writeln!(w)?; writeln!(w)?;
@ -221,7 +221,7 @@ mod gen {
writeln!(w, "/// The {} module.", usart.name)?; writeln!(w, "/// The {} module.", usart.name)?;
writeln!(w, "pub struct {};", usart.name)?; writeln!(w, "pub struct {};", usart.name)?;
writeln!(w)?; writeln!(w)?;
writeln!(w, "impl HardwareUsart for {} {{", usart.name)?; writeln!(w, "impl modules::HardwareUsart for {} {{", usart.name)?;
for register in usart.registers.iter() { for register in usart.registers.iter() {
let reg_ty = if register.name.starts_with("UDR") { // the data register. let reg_ty = if register.name.starts_with("UDR") { // the data register.
"DataRegister".to_owned() "DataRegister".to_owned()
@ -276,6 +276,41 @@ mod gen {
writeln!(w, "}}")?; writeln!(w, "}}")?;
} }
if let Some(tc) = mcu.module("TC16") { // Timer/Counter, 16-bit.
const TYPE_NAME: &'static str = "Timer16";
let find_reg = |name: &'static str| {
tc.registers().find(|r| r.name.starts_with(name))
.expect(&format!("could not find '{}' register", name))
};
let find_reg_suffix = |name: &'static str, suffix: &'static str| {
tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
.expect(&format!("could not find '{}' register", name))
};
writeln!(w, "/// 16-bit timer.")?;
writeln!(w, "pub struct {};", TYPE_NAME)?;
writeln!(w)?;
writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?;
writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?;
writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
writeln!(w, " const CS0: Mask<u8, Self::ControlB> = Self::ControlB::CS10;")?;
writeln!(w, " const CS1: Mask<u8, Self::ControlB> = Self::ControlB::CS11;")?;
writeln!(w, " const CS2: Mask<u8, Self::ControlB> = Self::ControlB::CS12;")?;
writeln!(w, " const WGM0: Mask<u8, Self::ControlA> = Self::ControlA::WGM10;")?;
writeln!(w, " const WGM1: Mask<u8, Self::ControlA> = Self::ControlA::WGM11;")?;
writeln!(w, " const WGM2: Mask<u8, Self::ControlB> = Self::ControlB::WGM10;")?;
writeln!(w, " const WGM3: Mask<u8, Self::ControlB> = Self::ControlB::WGM11;")?;
writeln!(w, " const OCIEA: Bitset<u8, Self::InterruptMask> = Self::InterruptMask::OCIE1A;")?;
writeln!(w, "}}")?;
}
Ok(()) Ok(())
} }

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@ -15,7 +15,6 @@
pub use self::register::{Bitset, Mask, Register, RegisterValue}; pub use self::register::{Bitset, Mask, Register, RegisterValue};
pub use self::pin::Pin; pub use self::pin::Pin;
pub use self::usart::HardwareUsart;
pub mod prelude; pub mod prelude;
pub mod serial; pub mod serial;
@ -26,7 +25,6 @@ pub mod config;
mod register; mod register;
mod pin; mod pin;
mod usart;
#[doc(hidden)] #[doc(hidden)]
pub mod std_stub; pub mod std_stub;

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@ -2,7 +2,9 @@
pub use self::spi::HardwareSpi; pub use self::spi::HardwareSpi;
pub use self::timer::{Timer8, Timer8Setup, Timer16, Timer16Setup}; pub use self::timer::{Timer8, Timer8Setup, Timer16, Timer16Setup};
pub use self::usart::HardwareUsart;
mod spi; mod spi;
mod timer; mod timer;
mod usart;

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@ -48,9 +48,11 @@ pub trait Timer16 {
const WGM0: Mask<u8, Self::ControlA>; const WGM0: Mask<u8, Self::ControlA>;
const WGM1: Mask<u8, Self::ControlA>; const WGM1: Mask<u8, Self::ControlA>;
const WGM2: Mask<u8, Self::ControlB>; const WGM2: Mask<u8, Self::ControlB>;
const WGM3: Mask<u8, Self::ControlB>; // fixme: right reg? const WGM3: Mask<u8, Self::ControlB>;
const OCIEA: Bitset<u8, Self::InterruptMask>; const OCIEA: Bitset<u8, Self::InterruptMask>;
fn setup() -> Timer16Setup<T> { Timer16Setup::new() }
} }
pub enum ClockSource { pub enum ClockSource {
@ -152,7 +154,7 @@ pub struct Timer16Setup<T: Timer16> {
impl<T: Timer16> Timer16Setup<T> { impl<T: Timer16> Timer16Setup<T> {
#[inline] #[inline]
pub fn new() -> Self { fn new() -> Self {
Timer16Setup { Timer16Setup {
a: Mask::zero(), a: Mask::zero(),
b: Mask::zero(), b: Mask::zero(),
@ -190,7 +192,6 @@ impl<T: Timer16> Timer16Setup<T> {
#[inline] #[inline]
pub fn configure(self) { pub fn configure(self) {
unsafe {
T::ControlA::write(self.a); T::ControlA::write(self.a);
T::ControlB::write(self.b); T::ControlB::write(self.b);
T::ControlC::write(self.c); T::ControlC::write(self.c);
@ -203,9 +204,7 @@ impl<T: Timer16> Timer16Setup<T> {
T::CompareA::write(v); T::CompareA::write(v);
// Enable compare interrupt // Enable compare interrupt
// FIXME: uncomment T::OCIEA.set_all();
// write_volatile(TIMSK1, OCIE1A);
}
} }
} }
} }

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@ -165,7 +165,6 @@ impl<T: Timer8> Timer8Setup<T> {
#[inline] #[inline]
pub fn configure(self) { pub fn configure(self) {
unsafe {
T::ControlA::write(self.a); T::ControlA::write(self.a);
T::ControlB::write(self.b); T::ControlB::write(self.b);
@ -177,9 +176,7 @@ impl<T: Timer8> Timer8Setup<T> {
T::CompareA::write(v); T::CompareA::write(v);
// Enable compare interrupt // Enable compare interrupt
// FIXME: is this right?
T::OCIEA.set_all(); T::OCIEA.set_all();
} }
} }
} }
}