Implement the Timer16 trait
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parent
d125f69f7d
commit
0157a8553c
39
build.rs
39
build.rs
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@ -71,7 +71,7 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
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fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
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writeln!(w, "//! Core for {}.", mcu.device.name)?;
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writeln!(w, "//! Core for {}.", mcu.device.name)?;
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writeln!(w)?;
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writeln!(w)?;
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writeln!(w, "use {{Mask, Bitset, HardwareUsart, Register}};")?;
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writeln!(w, "use {{Mask, Bitset, Register}};")?;
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writeln!(w, "use modules;")?;
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writeln!(w, "use modules;")?;
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writeln!(w)?;
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writeln!(w)?;
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@ -221,7 +221,7 @@ mod gen {
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writeln!(w, "/// The {} module.", usart.name)?;
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writeln!(w, "/// The {} module.", usart.name)?;
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writeln!(w, "pub struct {};", usart.name)?;
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writeln!(w, "pub struct {};", usart.name)?;
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writeln!(w)?;
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writeln!(w)?;
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writeln!(w, "impl HardwareUsart for {} {{", usart.name)?;
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writeln!(w, "impl modules::HardwareUsart for {} {{", usart.name)?;
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for register in usart.registers.iter() {
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for register in usart.registers.iter() {
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let reg_ty = if register.name.starts_with("UDR") { // the data register.
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let reg_ty = if register.name.starts_with("UDR") { // the data register.
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"DataRegister".to_owned()
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"DataRegister".to_owned()
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@ -276,6 +276,41 @@ mod gen {
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writeln!(w, "}}")?;
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writeln!(w, "}}")?;
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}
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}
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if let Some(tc) = mcu.module("TC16") { // Timer/Counter, 16-bit.
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const TYPE_NAME: &'static str = "Timer16";
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let find_reg = |name: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name))
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.expect(&format!("could not find '{}' register", name))
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};
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let find_reg_suffix = |name: &'static str, suffix: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
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.expect(&format!("could not find '{}' register", name))
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};
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writeln!(w, "/// 16-bit timer.")?;
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writeln!(w, "pub struct {};", TYPE_NAME)?;
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writeln!(w)?;
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writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?;
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writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
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writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
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writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
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writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
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writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
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writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?;
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writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
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writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
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writeln!(w, " const CS0: Mask<u8, Self::ControlB> = Self::ControlB::CS10;")?;
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writeln!(w, " const CS1: Mask<u8, Self::ControlB> = Self::ControlB::CS11;")?;
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writeln!(w, " const CS2: Mask<u8, Self::ControlB> = Self::ControlB::CS12;")?;
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writeln!(w, " const WGM0: Mask<u8, Self::ControlA> = Self::ControlA::WGM10;")?;
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writeln!(w, " const WGM1: Mask<u8, Self::ControlA> = Self::ControlA::WGM11;")?;
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writeln!(w, " const WGM2: Mask<u8, Self::ControlB> = Self::ControlB::WGM10;")?;
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writeln!(w, " const WGM3: Mask<u8, Self::ControlB> = Self::ControlB::WGM11;")?;
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writeln!(w, " const OCIEA: Bitset<u8, Self::InterruptMask> = Self::InterruptMask::OCIE1A;")?;
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writeln!(w, "}}")?;
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}
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Ok(())
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Ok(())
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}
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}
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@ -15,7 +15,6 @@
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pub use self::register::{Bitset, Mask, Register, RegisterValue};
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pub use self::register::{Bitset, Mask, Register, RegisterValue};
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pub use self::pin::Pin;
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pub use self::pin::Pin;
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pub use self::usart::HardwareUsart;
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pub mod prelude;
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pub mod prelude;
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pub mod serial;
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pub mod serial;
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@ -26,7 +25,6 @@ pub mod config;
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mod register;
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mod register;
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mod pin;
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mod pin;
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mod usart;
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#[doc(hidden)]
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#[doc(hidden)]
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pub mod std_stub;
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pub mod std_stub;
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@ -2,7 +2,9 @@
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pub use self::spi::HardwareSpi;
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pub use self::spi::HardwareSpi;
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pub use self::timer::{Timer8, Timer8Setup, Timer16, Timer16Setup};
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pub use self::timer::{Timer8, Timer8Setup, Timer16, Timer16Setup};
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pub use self::usart::HardwareUsart;
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mod spi;
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mod spi;
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mod timer;
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mod timer;
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mod usart;
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@ -48,9 +48,11 @@ pub trait Timer16 {
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const WGM0: Mask<u8, Self::ControlA>;
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const WGM0: Mask<u8, Self::ControlA>;
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const WGM1: Mask<u8, Self::ControlA>;
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const WGM1: Mask<u8, Self::ControlA>;
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const WGM2: Mask<u8, Self::ControlB>;
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const WGM2: Mask<u8, Self::ControlB>;
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const WGM3: Mask<u8, Self::ControlB>; // fixme: right reg?
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const WGM3: Mask<u8, Self::ControlB>;
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const OCIEA: Bitset<u8, Self::InterruptMask>;
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const OCIEA: Bitset<u8, Self::InterruptMask>;
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fn setup() -> Timer16Setup<T> { Timer16Setup::new() }
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}
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}
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pub enum ClockSource {
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pub enum ClockSource {
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@ -152,7 +154,7 @@ pub struct Timer16Setup<T: Timer16> {
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impl<T: Timer16> Timer16Setup<T> {
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impl<T: Timer16> Timer16Setup<T> {
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#[inline]
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#[inline]
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pub fn new() -> Self {
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fn new() -> Self {
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Timer16Setup {
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Timer16Setup {
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a: Mask::zero(),
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a: Mask::zero(),
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b: Mask::zero(),
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b: Mask::zero(),
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@ -190,7 +192,6 @@ impl<T: Timer16> Timer16Setup<T> {
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#[inline]
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#[inline]
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pub fn configure(self) {
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pub fn configure(self) {
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unsafe {
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T::ControlA::write(self.a);
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T::ControlA::write(self.a);
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T::ControlB::write(self.b);
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T::ControlB::write(self.b);
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T::ControlC::write(self.c);
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T::ControlC::write(self.c);
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@ -203,9 +204,7 @@ impl<T: Timer16> Timer16Setup<T> {
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T::CompareA::write(v);
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T::CompareA::write(v);
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// Enable compare interrupt
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// Enable compare interrupt
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// FIXME: uncomment
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T::OCIEA.set_all();
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// write_volatile(TIMSK1, OCIE1A);
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}
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}
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}
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}
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}
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}
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}
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@ -165,7 +165,6 @@ impl<T: Timer8> Timer8Setup<T> {
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#[inline]
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#[inline]
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pub fn configure(self) {
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pub fn configure(self) {
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unsafe {
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T::ControlA::write(self.a);
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T::ControlA::write(self.a);
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T::ControlB::write(self.b);
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T::ControlB::write(self.b);
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@ -177,9 +176,7 @@ impl<T: Timer8> Timer8Setup<T> {
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T::CompareA::write(v);
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T::CompareA::write(v);
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// Enable compare interrupt
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// Enable compare interrupt
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// FIXME: is this right?
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T::OCIEA.set_all();
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T::OCIEA.set_all();
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}
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}
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}
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}
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}
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}
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}
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