savanni
/
ruduino
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Compare commits

merge into: savanni:main
Branches Tags
savanni:main
savanni:attiny85
savanni:expanded-spi-pins
...
pull from: savanni:attiny85
Branches Tags
savanni:attiny85
savanni:expanded-spi-pins
savanni:main

4 Commits
main ... attiny85

Author SHA1 Message Date
Savanni D'Gerinel bda8637c08 Allow passing an MCU description to reprocess just that one file. 
This is a useful convenience for debugging one particular processor
 2023-04-02 13:20:16 -04:00
Savanni D'Gerinel f17af2ba44 Resolve ambiguities with the timer/counter code 
The goal was to add attiny85, but this ended up adding a lot more, too. The problem was with the TC16 module, which seems to be a bit ambiguous between the hardware description file and the datasheet.
 2023-04-02 13:14:50 -04:00
Savanni D'Gerinel 8235d34f95 Add CS, PDI, and PDO pins 
This has the side effect of adding atmega32u4 and atmega16u4
 2023-04-02 11:37:13 -04:00
Savanni D'Gerinel f516e1216b Rename MISO/MOSI to SerialDataIn and SerialDataOut 2023-04-02 11:35:35 -04:00
39 changed files with 28556 additions and 220 deletions
Show Stats Expand all files Collapse all files

337
core_generator/src/gen.rs
View File

@ -1,13 +1,17 @@
use avr_mcu::*;
use std::io;
use std::io::prelude::*;
use std::{
collections::HashMap,
io::{self, prelude::*},
};
pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
for register in mcu.registers() {
let ty = if register.size == 1 { "u8" } else { "u16" };
// HACK: Skip, atmeg328p pack defines two of these.
if register.name == "GTCCR" { continue; }
if register.name == "GTCCR" {
continue;
}
writeln!(w, "#[allow(non_camel_case_types)]")?;
writeln!(w, "pub struct {};", register.name)?;
@ -16,7 +20,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
writeln!(w, "impl {} {{", register.name)?;
for bitfield in register.bitfields.iter() {
// Create a mask for the whole bitset.
writeln!(w, " pub const {}: RegisterBits<Self> = RegisterBits::new(0x{:x});", bitfield.name, bitfield.mask)?;
writeln!(
w,
" pub const {}: RegisterBits<Self> = RegisterBits::new(0x{:x});",
bitfield.name, bitfield.mask
)?;
// We create masks for the individual bits in the field if there
// is more than one bit in the field.
@ -24,8 +32,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
let mut current_mask_bit_num = 0;
for current_register_bit_num in 0..15 {
if (current_mask & 0b1) == 0b1 {
writeln!(w, " pub const {}{}: RegisterBits<Self> = RegisterBits::new(1<<{});",
bitfield.name, current_mask_bit_num, current_register_bit_num)?;
writeln!(
w,
" pub const {}{}: RegisterBits<Self> = RegisterBits::new(1<<{});",
bitfield.name, current_mask_bit_num, current_register_bit_num
)?;
current_mask_bit_num += 1;
}
@ -38,7 +49,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
writeln!(w, "impl Register for {} {{", register.name)?;
writeln!(w, " type T = {};", ty)?;
writeln!(w, " const ADDRESS: *mut {} = 0x{:x} as *mut {};", ty, register.offset, ty)?;
writeln!(
w,
" const ADDRESS: *mut {} = 0x{:x} as *mut {};",
ty, register.offset, ty
)?;
writeln!(w, "}}")?;
}
@ -61,9 +76,14 @@ pub fn write_pins(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
let idx = signal.index.expect("signal with no index");
let struct_name = format!("{}{}", port_letter, idx);
let io_module = mcu.modules.iter().find(|m| m.name == "PORT")
let io_module = mcu
.modules
.iter()
.find(|m| m.name == "PORT")
.expect("no port io module defined for this port");
let register_group = io_module.register_groups.iter()
let register_group = io_module
.register_groups
.iter()
.find(|rg| rg.name == instance.name)
.expect("no register group defined for this port");
@ -90,30 +110,52 @@ pub fn write_pins(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
Ok(())
}
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
enum SpiPinType {
SerialDataIn,
SerialDataOut,
Clock,
ChipSelect,
}
pub fn write_spi_modules(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
if let Some(module) = mcu.module("SPI") {
let peripheral = mcu.peripheral("SPI").expect("found SPI module but no peripheral");
let peripheral = mcu
.peripheral("SPI")
.expect("found SPI module but no peripheral");
let port_peripheral = mcu.port_peripheral();
writeln!(w, "pub struct Spi;")?;
writeln!(w)?;
writeln!(w, "impl modules::HardwareSpi for Spi {{")?;
let mut pins: HashMap<SpiPinType, String> = HashMap::new();
for spi_signal in peripheral.signals() {
let spi_signal_name = spi_signal.group.clone().expect("spi signal does not have group name");
let (port_instance, port_signal) = port_peripheral.instance_signal_with_pad(&spi_signal.pad)
let spi_signal_name = spi_signal
.group
.clone()
.expect("spi signal does not have group name");
let (port_instance, port_signal) = port_peripheral
.instance_signal_with_pad(&spi_signal.pad)
.expect("no port signal associated with the spi signal pad");
let pin_name = self::pin_name(port_instance, port_signal);
let const_name = match &spi_signal_name[..] {
"MISO" => "MasterInSlaveOut",
"MOSI" => "MasterOutSlaveIn",
"SCK" => "Clock",
"SS" => "SlaveSelect",
"MISO" => SpiPinType::SerialDataIn,
"MOSI" => SpiPinType::SerialDataOut,
"SCK" => SpiPinType::Clock,
"SS" => SpiPinType::ChipSelect,
"CS" => SpiPinType::ChipSelect,
"PDI" => SpiPinType::SerialDataOut,
"PDO" => SpiPinType::SerialDataIn,
_ => panic!("unknown spi signal name: '{}'", spi_signal_name),
};
writeln!(w, " type {} = {};", const_name, pin_name)?;
pins.insert(const_name, pin_name);
}
for (pin_type, pin_name) in pins.into_iter() {
writeln!(w, " type {:?} = {};", pin_type, pin_name)?;
}
for reg in module.registers() {
@ -140,12 +182,15 @@ pub fn write_usarts(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
writeln!(w)?;
writeln!(w, "impl modules::HardwareUsart for {} {{", usart.name)?;
for register in usart.registers.iter() {
let reg_ty = if register.name.starts_with("UDR") { // the data register.
let reg_ty = if register.name.starts_with("UDR") {
// the data register.
"DataRegister".to_owned()
} else if register.name.starts_with("UCSR") { // one of the three control/status registers.
} else if register.name.starts_with("UCSR") {
// one of the three control/status registers.
let suffix = register.name.chars().rev().next().unwrap();
format!("ControlRegister{}", suffix)
} else if register.name.starts_with("UBRR") { // the baud rate register.
} else if register.name.starts_with("UBRR") {
// the baud rate register.
"BaudRateRegister".to_owned()
} else {
panic!("unknown usart register '{}'", register.name);
@ -160,85 +205,195 @@ pub fn write_usarts(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
}
pub fn write_timers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
if let Some(tc) = mcu.module("TC8") { // Timer/Counter, 8-bit.
const TYPE_NAME: &'static str = "Timer8";
let find_reg = |name: &'static str| {
tc.registers().find(|r| r.name.starts_with(name))
.expect(&format!("could not find '{}' register", name))
let find_reg = |group: &RegisterGroup, name: &'static str| {
group
.registers
.iter()
.find(|r| r.name.starts_with(name))
.expect(&format!("could not find '{}' register", name))
.clone()
};
let find_reg_suffix_optional =
|group: &RegisterGroup, name: &'static str, suffix: &'static str| {
group
.registers
.iter()
.find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
.cloned()
};
let find_reg_suffix_optional = |name: &'static str, suffix: &'static str| {
tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
};
let find_reg_suffix = |name: &'static str, suffix: &'static str| {
find_reg_suffix_optional(name, suffix)
.expect(&format!("could not find '{}' register", name))
};
let timer_number = find_reg("TIMSK").name.chars().last().unwrap()
.to_digit(10).unwrap();
let find_reg_suffix = |group: &RegisterGroup, name: &'static str, suffix: &'static str| {
find_reg_suffix_optional(group, name, suffix)
.expect(&format!("could not find '{} {}' register", name, suffix))
.clone()
};
// TODO: At the moment, we do not support 8 bit timers that don't have two compare
// registers.
let should_skip_timer = find_reg_suffix_optional("OCR", "B").is_none();
if let Some(tc) = mcu.module("TC8") {
for group in tc.register_groups.iter() {
let timer_number = group.name.chars().last().unwrap().to_digit(10).unwrap();
if !should_skip_timer {
writeln!(w, "/// 8-bit timer.")?;
writeln!(w, "pub struct {};", TYPE_NAME)?;
writeln!(w)?;
writeln!(w, "impl modules::Timer8 for {} {{", TYPE_NAME)?;
writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
writeln!(w, " const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS00;")?;
writeln!(w, " const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS01;")?;
writeln!(w, " const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS02;")?;
writeln!(w, " const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM00;")?;
writeln!(w, " const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM01;")?;
writeln!(w, " const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM020;")?;
writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
writeln!(w, "}}")?;
// Timer/Counter, 8-bit.
const TYPE_NAME: &'static str = "Timer8";
// TODO: At the moment, we do not support 8 bit timers that don't have two compare
// registers.
let should_skip_timer = find_reg_suffix_optional(&group, "OCR", "B").is_none();
if !should_skip_timer {
writeln!(w, "/// 8-bit timer.")?;
writeln!(w, "pub struct {};", TYPE_NAME)?;
writeln!(w)?;
writeln!(w, "impl modules::Timer8 for {} {{", TYPE_NAME)?;
writeln!(
w,
" type CompareA = {};",
find_reg_suffix(&group, "OCR", "A").name
)?;
writeln!(
w,
" type CompareB = {};",
find_reg_suffix(&group, "OCR", "B").name
)?;
writeln!(w, " type Counter = {};", find_reg(&group, "TCNT").name)?;
writeln!(
w,
" type ControlA = {};",
find_reg_suffix(&group, "TCCR", "A").name
)?;
writeln!(
w,
" type ControlB = {};",
find_reg_suffix(&group, "TCCR", "B").name
)?;
writeln!(
w,
" type InterruptMask = {};",
find_reg(&group, "TIMSK").name
)?;
writeln!(
w,
" type InterruptFlag = {};",
find_reg(&group, "TIFR").name
)?;
writeln!(
w,
" const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS00;"
)?;
writeln!(
w,
" const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS01;"
)?;
writeln!(
w,
" const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS02;"
)?;
writeln!(
w,
" const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM00;"
)?;
writeln!(
w,
" const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM01;"
)?;
writeln!(
w,
" const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM020;"
)?;
writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
writeln!(w, "}}")?;
}
}
}
if let Some(tc) = mcu.module("TC16") { // Timer/Counter, 16-bit.
const TYPE_NAME: &'static str = "Timer16";
if let Some(tc) = mcu.module("TC16") {
for group in tc.register_groups.iter() {
let timer_number = group.name.chars().last().unwrap().to_digit(10).unwrap();
let find_reg = |name: &'static str| {
tc.registers().find(|r| r.name.starts_with(name))
.expect(&format!("could not find '{}' register", name))
};
let find_reg_suffix = |name: &'static str, suffix: &'static str| {
tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
.expect(&format!("could not find '{}' register", name))
};
let timer_number = find_reg("TIMSK").name.chars().last().unwrap()
.to_digit(10).unwrap();
if find_reg_suffix_optional(&group, "TCCR", "A").is_none() {
// ATTiny85 has a TC16 group set in the data file, but there's no 16 bit timer
// documented in the datasheet. As such, I have no idea what to do about the three
// control registers and am simply going to bail instead of making assumptions.
println!("Only one control register found for 16-bit counter. Skipping.");
continue;
}
writeln!(w, "/// 16-bit timer.")?;
writeln!(w, "pub struct {};", TYPE_NAME)?;
writeln!(w)?;
writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?;
writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?;
writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
writeln!(w, " const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS10;")?;
writeln!(w, " const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS11;")?;
writeln!(w, " const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS12;")?;
writeln!(w, " const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM10;")?;
writeln!(w, " const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM11;")?;
writeln!(w, " const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM10;")?;
writeln!(w, " const WGM3: RegisterBits<Self::ControlB> = Self::ControlB::WGM11;")?;
writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
writeln!(w, "}}")?;
// Timer/Counter, 16-bit.
const TYPE_NAME: &'static str = "Timer16";
writeln!(w, "/// 16-bit timer.")?;
writeln!(w, "pub struct {};", TYPE_NAME)?;
writeln!(w)?;
writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?;
writeln!(
w,
" type CompareA = {};",
find_reg_suffix(&group, "OCR", "A").name
)?;
writeln!(
w,
" type CompareB = {};",
find_reg_suffix(&group, "OCR", "B").name
)?;
writeln!(w, " type Counter = {};", find_reg(&group, "TCNT").name)?;
writeln!(
w,
" type ControlA = {};",
find_reg_suffix(&group, "TCCR", "A").name
)?;
writeln!(
w,
" type ControlB = {};",
find_reg_suffix(&group, "TCCR", "B").name
)?;
writeln!(
w,
" type ControlC = {};",
find_reg_suffix(&group, "TCCR", "C").name
)?;
writeln!(
w,
" type InterruptMask = {};",
find_reg(&group, "TIMSK").name
)?;
writeln!(
w,
" type InterruptFlag = {};",
find_reg(&group, "TIFR").name
)?;
writeln!(
w,
" const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS10;"
)?;
writeln!(
w,
" const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS11;"
)?;
writeln!(
w,
" const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS12;"
)?;
writeln!(
w,
" const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM10;"
)?;
writeln!(
w,
" const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM11;"
)?;
writeln!(
w,
" const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM10;"
)?;
writeln!(
w,
" const WGM3: RegisterBits<Self::ControlB> = Self::ControlB::WGM11;"
)?;
writeln!(
w,
" const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;",
timer_number
)?;
writeln!(w, "}}")?;
}
}
Ok(())

59
core_generator/src/main.rs
View File

@ -116,7 +116,9 @@ const DISABLE_FOR_DEVICES: &'static [&'static str] = &[
fn base_output_path() -> PathBuf {
match std::env::args().skip(1).next() {
Some(path) => Path::new(&path).to_owned(),
None => panic!("please pass a destination path for the generated cores on the command line"),
None => {
panic!("please pass a destination path for the generated cores on the command line")
}
}
}
@ -137,17 +139,32 @@ fn main() {
fs::create_dir_all(&cores_path()).expect("could not create cores directory");
}
let microcontrollers = avr_mcu::microcontrollers();
let (count_total, mut cores_successful, mut cores_failed) = (microcontrollers.len(), Vec::new(), Vec::new());
let args: Vec<String> = std::env::args().collect();
println!("args: {:?}", args);
let microcontrollers = if args.len() > 2 {
vec![avr_mcu::microcontroller(args[2].as_ref())]
} else {
Vec::from(avr_mcu::microcontrollers())
};
let (count_total, mut cores_successful, mut cores_failed) =
(microcontrollers.len(), Vec::new(), Vec::new());
for (i, mcu) in microcontrollers.iter().enumerate() {
if DISABLE_FOR_DEVICES.iter().any(|d| mcu.device.name == *d || core_module_name(mcu) == *d) {
if DISABLE_FOR_DEVICES
.iter()
.any(|d| mcu.device.name == *d || core_module_name(mcu) == *d)
{
println!("skipping generation of core for '{}'", mcu.device.name);
continue;
}
let result = std::panic::catch_unwind(|| {
println!("generating core for '{}' ({} of {})", mcu.device.name, i + 1, count_total);
println!(
"generating core for '{}' ({} of {})",
mcu.device.name,
i + 1,
count_total
);
generate_cores(&[mcu.clone()]).unwrap();
});
@ -155,7 +172,7 @@ fn main() {
Ok(..) => {
println!("successfully generated core for '{}'", mcu.device.name);
cores_successful.push(mcu);
},
}
Err(e) => {
delete_core_module(mcu).unwrap(); // Don't leave around broken core files.
@ -165,12 +182,18 @@ fn main() {
String::new()
};
eprintln!("failed to generate core for '{}', skipping: {}\n", mcu.device.name, error_message);
eprintln!(
"failed to generate core for '{}', skipping: {}\n",
mcu.device.name, error_message
);
cores_failed.push(mcu);
},
}
}
}
println!("generating 'src/cores/mod.rs' for the {} successfully generated cores", cores_successful.len());
println!(
"generating 'src/cores/mod.rs' for the {} successfully generated cores",
cores_successful.len()
);
generate_cores_mod_rs(&cores_successful[..]).expect("failed to generates src/cores/mod.rs");
println!("statistics:");
@ -201,7 +224,10 @@ fn generate_cores_mod_rs(mcus: &[&Mcu]) -> Result<(), io::Error> {
let path = cores_path().join("mod.rs");
let mut w = File::create(&path)?;
writeln!(w, "//! The primary module containing microcontroller-specific core definitions")?;
writeln!(
w,
"//! The primary module containing microcontroller-specific core definitions"
)?;
writeln!(w)?;
for mcu in mcus {
@ -224,9 +250,17 @@ fn generate_cores_mod_rs(mcus: &[&Mcu]) -> Result<(), io::Error> {
writeln!(w, "///\n/// This device is chosen as the default when the crate is targeting non-AVR devices.")?;
}
writeln!(w, "#[cfg(any(avr_mcu_{}, feature = \"all-mcus\"{}))] pub mod {};", module_name, cfg_check_default_fallback, module_name)?;
writeln!(
w,
"#[cfg(any(avr_mcu_{}, feature = \"all-mcus\"{}))] pub mod {};",
module_name, cfg_check_default_fallback, module_name
)?;
writeln!(w, "#[cfg({})] pub use self::{} as current;", current_module_check, module_name)?;
writeln!(
w,
"#[cfg({})] pub use self::{} as current;",
current_module_check, module_name
)?;
writeln!(w)?;
}
writeln!(w)
@ -246,4 +280,3 @@ fn write_core_module(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
writeln!(w)
}

2
regenerate-cores.sh
View File

@ -6,5 +6,5 @@ SCRIPT_DIR=$(dirname $0)
cd "${SCRIPT_DIR}/core_generator"
cargo run "../src"
cargo run -- ../src $1

1857
src/cores/at90pwm161.rs Normal file
View File

File diff suppressed because it is too large Load Diff

6
src/cores/atmega168.rs
View File

@ -1791,9 +1791,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type SerialDataOut = port::B3;
type ChipSelect = port::B2;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega168a.rs
View File

@ -1794,10 +1794,10 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type Clock = port::B5;
type SerialDataIn = port::B4;
type SerialDataOut = port::B3;
type ChipSelect = port::B2;
type DataRegister = SPDR;
type StatusRegister = SPSR;
type ControlRegister = SPCR;

6
src/cores/atmega168p.rs
View File

@ -1800,9 +1800,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type ChipSelect = port::B2;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega168pa.rs
View File

@ -1800,9 +1800,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type SerialDataOut = port::B3;
type ChipSelect = port::B2;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

3399
src/cores/atmega16u4.rs Normal file
View File

File diff suppressed because it is too large Load Diff

6
src/cores/atmega328.rs
View File

@ -2040,9 +2040,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type SerialDataIn = port::B4;
type SerialDataOut = port::B3;
type ChipSelect = port::B2;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega328p.rs
View File

@ -1800,9 +1800,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

3044
src/cores/atmega32u4.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1389
src/cores/atmega406.rs Normal file
View File

File diff suppressed because it is too large Load Diff

6
src/cores/atmega48.rs
View File

@ -1773,9 +1773,9 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type ChipSelect = port::B2;
type Clock = port::B5;
type DataRegister = SPDR;
type StatusRegister = SPSR;

6
src/cores/atmega48a.rs
View File

@ -1798,10 +1798,10 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type Clock = port::B5;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type DataRegister = SPDR;
type StatusRegister = SPSR;
type ControlRegister = SPCR;

6
src/cores/atmega48p.rs
View File

@ -1779,10 +1779,10 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type SerialDataIn = port::B4;
type ChipSelect = port::B2;
type Clock = port::B5;
type SerialDataOut = port::B3;
type DataRegister = SPDR;
type StatusRegister = SPSR;
type ControlRegister = SPCR;

6
src/cores/atmega48pa.rs
View File

@ -1804,10 +1804,10 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type ChipSelect = port::B2;
type Clock = port::B5;
type SerialDataIn = port::B4;
type SerialDataOut = port::B3;
type DataRegister = SPDR;
type StatusRegister = SPSR;
type ControlRegister = SPCR;

6
src/cores/atmega88.rs
View File

@ -1791,10 +1791,10 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type SerialDataIn = port::B4;
type Clock = port::B5;
type ChipSelect = port::B2;
type SerialDataOut = port::B3;
type DataRegister = SPDR;
type StatusRegister = SPSR;
type ControlRegister = SPCR;

6
src/cores/atmega88a.rs
View File

@ -1794,10 +1794,10 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type Clock = port::B5;
type SerialDataOut = port::B3;
type SerialDataIn = port::B4;
type ChipSelect = port::B2;
type DataRegister = SPDR;
type StatusRegister = SPSR;
type ControlRegister = SPCR;

6
src/cores/atmega88p.rs
View File

@ -1797,10 +1797,10 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type Clock = port::B5;
type ChipSelect = port::B2;
type SerialDataIn = port::B4;
type SerialDataOut = port::B3;
type DataRegister = SPDR;
type StatusRegister = SPSR;
type ControlRegister = SPCR;

6
src/cores/atmega88pa.rs
View File

@ -1800,10 +1800,10 @@ pub mod port {
pub struct Spi;
impl modules::HardwareSpi for Spi {
type SlaveSelect = port::B2;
type MasterOutSlaveIn = port::B3;
type MasterInSlaveOut = port::B4;
type Clock = port::B5;
type ChipSelect = port::B2;
type SerialDataIn = port::B4;
type SerialDataOut = port::B3;
type DataRegister = SPDR;
type StatusRegister = SPSR;
type ControlRegister = SPCR;

282
src/cores/attiny11.rs Normal file
View File

@ -0,0 +1,282 @@
//! Core for ATtiny11.
use crate::{modules, RegisterBits, Register};
#[allow(non_camel_case_types)]
pub struct LOW;
impl LOW {
pub const FSTRT: RegisterBits<Self> = RegisterBits::new(0x10);
pub const FSTRT0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const RSTDISBL: RegisterBits<Self> = RegisterBits::new(0x8);
pub const RSTDISBL0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const CKSEL: RegisterBits<Self> = RegisterBits::new(0x7);
pub const CKSEL0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const CKSEL1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const CKSEL2: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for LOW {
type T = u8;
const ADDRESS: *mut u8 = 0x0 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct LOCKBIT;
impl LOCKBIT {
pub const LB: RegisterBits<Self> = RegisterBits::new(0x6);
pub const LB0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const LB1: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for LOCKBIT {
type T = u8;
const ADDRESS: *mut u8 = 0x0 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct ACSR;
impl ACSR {
pub const ACD: RegisterBits<Self> = RegisterBits::new(0x80);
pub const ACD0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const ACO: RegisterBits<Self> = RegisterBits::new(0x20);
pub const ACO0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const ACI: RegisterBits<Self> = RegisterBits::new(0x10);
pub const ACI0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const ACIE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const ACIE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const ACIS: RegisterBits<Self> = RegisterBits::new(0x3);
pub const ACIS0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const ACIS1: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for ACSR {
type T = u8;
const ADDRESS: *mut u8 = 0x8 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct GIMSK;
impl GIMSK {
pub const INT0: RegisterBits<Self> = RegisterBits::new(0x40);
pub const INT00: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const PCIE: RegisterBits<Self> = RegisterBits::new(0x20);
pub const PCIE0: RegisterBits<Self> = RegisterBits::new(1<<5);
}
impl Register for GIMSK {
type T = u8;
const ADDRESS: *mut u8 = 0x3b as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct GIFR;
impl GIFR {
pub const INTF0: RegisterBits<Self> = RegisterBits::new(0x40);
pub const INTF00: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const PCIF: RegisterBits<Self> = RegisterBits::new(0x20);
pub const PCIF0: RegisterBits<Self> = RegisterBits::new(1<<5);
}
impl Register for GIFR {
type T = u8;
const ADDRESS: *mut u8 = 0x3a as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PORTB;
impl PORTB {
}
impl Register for PORTB {
type T = u8;
const ADDRESS: *mut u8 = 0x18 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct DDRB;
impl DDRB {
}
impl Register for DDRB {
type T = u8;
const ADDRESS: *mut u8 = 0x17 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PINB;
impl PINB {
}
impl Register for PINB {
type T = u8;
const ADDRESS: *mut u8 = 0x16 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TIMSK;
impl TIMSK {
pub const TOIE0: RegisterBits<Self> = RegisterBits::new(0x2);
pub const TOIE00: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for TIMSK {
type T = u8;
const ADDRESS: *mut u8 = 0x39 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TIFR;
impl TIFR {
pub const TOV0: RegisterBits<Self> = RegisterBits::new(0x2);
pub const TOV00: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for TIFR {
type T = u8;
const ADDRESS: *mut u8 = 0x38 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCCR0;
impl TCCR0 {
pub const CS02: RegisterBits<Self> = RegisterBits::new(0x4);
pub const CS020: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const CS01: RegisterBits<Self> = RegisterBits::new(0x2);
pub const CS010: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const CS00: RegisterBits<Self> = RegisterBits::new(0x1);
pub const CS000: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for TCCR0 {
type T = u8;
const ADDRESS: *mut u8 = 0x33 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCNT0;
impl TCNT0 {
}
impl Register for TCNT0 {
type T = u8;
const ADDRESS: *mut u8 = 0x32 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct WDTCR;
impl WDTCR {
pub const WDTOE: RegisterBits<Self> = RegisterBits::new(0x10);
pub const WDTOE0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const WDE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const WDE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const WDP: RegisterBits<Self> = RegisterBits::new(0x7);
pub const WDP0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const WDP1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const WDP2: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for WDTCR {
type T = u8;
const ADDRESS: *mut u8 = 0x21 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct SREG;
impl SREG {
pub const I: RegisterBits<Self> = RegisterBits::new(0x80);
pub const I0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const T: RegisterBits<Self> = RegisterBits::new(0x40);
pub const T0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const H: RegisterBits<Self> = RegisterBits::new(0x20);
pub const H0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const S: RegisterBits<Self> = RegisterBits::new(0x10);
pub const S0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const V: RegisterBits<Self> = RegisterBits::new(0x8);
pub const V0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const N: RegisterBits<Self> = RegisterBits::new(0x4);
pub const N0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const Z: RegisterBits<Self> = RegisterBits::new(0x2);
pub const Z0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const C: RegisterBits<Self> = RegisterBits::new(0x1);
pub const C0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for SREG {
type T = u8;
const ADDRESS: *mut u8 = 0x3f as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct MCUSR;
impl MCUSR {
pub const EXTRF: RegisterBits<Self> = RegisterBits::new(0x2);
pub const EXTRF0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const PORF: RegisterBits<Self> = RegisterBits::new(0x1);
pub const PORF0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for MCUSR {
type T = u8;
const ADDRESS: *mut u8 = 0x34 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct MCUCR;
impl MCUCR {
pub const SE: RegisterBits<Self> = RegisterBits::new(0x20);
pub const SE0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const SM: RegisterBits<Self> = RegisterBits::new(0x10);
pub const SM0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const ISC0: RegisterBits<Self> = RegisterBits::new(0x3);
pub const ISC00: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const ISC01: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for MCUCR {
type T = u8;
const ADDRESS: *mut u8 = 0x35 as *mut u8;
}
pub mod port {
#![allow(unused_imports)]
use super::*;
use crate::Pin;
}

363
src/cores/attiny12.rs Normal file
View File

@ -0,0 +1,363 @@
//! Core for ATtiny12.
use crate::{modules, RegisterBits, Register};
#[allow(non_camel_case_types)]
pub struct LOW;
impl LOW {
pub const BODLEVEL: RegisterBits<Self> = RegisterBits::new(0x80);
pub const BODLEVEL0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const BODEN: RegisterBits<Self> = RegisterBits::new(0x40);
pub const BODEN0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const SPIEN: RegisterBits<Self> = RegisterBits::new(0x20);
pub const SPIEN0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const RSTDISBL: RegisterBits<Self> = RegisterBits::new(0x10);
pub const RSTDISBL0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const CKSEL: RegisterBits<Self> = RegisterBits::new(0xf);
pub const CKSEL0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const CKSEL1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const CKSEL2: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const CKSEL3: RegisterBits<Self> = RegisterBits::new(1<<3);
}
impl Register for LOW {
type T = u8;
const ADDRESS: *mut u8 = 0x0 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct LOCKBIT;
impl LOCKBIT {
pub const LB: RegisterBits<Self> = RegisterBits::new(0x6);
pub const LB0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const LB1: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for LOCKBIT {
type T = u8;
const ADDRESS: *mut u8 = 0x0 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct ACSR;
impl ACSR {
pub const ACD: RegisterBits<Self> = RegisterBits::new(0x80);
pub const ACD0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const AINBG: RegisterBits<Self> = RegisterBits::new(0x40);
pub const AINBG0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const ACO: RegisterBits<Self> = RegisterBits::new(0x20);
pub const ACO0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const ACI: RegisterBits<Self> = RegisterBits::new(0x10);
pub const ACI0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const ACIE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const ACIE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const ACIS: RegisterBits<Self> = RegisterBits::new(0x3);
pub const ACIS0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const ACIS1: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for ACSR {
type T = u8;
const ADDRESS: *mut u8 = 0x8 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct SREG;
impl SREG {
pub const I: RegisterBits<Self> = RegisterBits::new(0x80);
pub const I0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const T: RegisterBits<Self> = RegisterBits::new(0x40);
pub const T0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const H: RegisterBits<Self> = RegisterBits::new(0x20);
pub const H0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const S: RegisterBits<Self> = RegisterBits::new(0x10);
pub const S0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const V: RegisterBits<Self> = RegisterBits::new(0x8);
pub const V0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const N: RegisterBits<Self> = RegisterBits::new(0x4);
pub const N0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const Z: RegisterBits<Self> = RegisterBits::new(0x2);
pub const Z0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const C: RegisterBits<Self> = RegisterBits::new(0x1);
pub const C0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for SREG {
type T = u8;
const ADDRESS: *mut u8 = 0x3f as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct MCUCR;
impl MCUCR {
pub const PUD: RegisterBits<Self> = RegisterBits::new(0x40);
pub const PUD0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const SE: RegisterBits<Self> = RegisterBits::new(0x20);
pub const SE0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const SM: RegisterBits<Self> = RegisterBits::new(0x10);
pub const SM0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const ISC0: RegisterBits<Self> = RegisterBits::new(0x3);
pub const ISC00: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const ISC01: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for MCUCR {
type T = u8;
const ADDRESS: *mut u8 = 0x35 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct MCUSR;
impl MCUSR {
pub const WDRF: RegisterBits<Self> = RegisterBits::new(0x8);
pub const WDRF0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const BORF: RegisterBits<Self> = RegisterBits::new(0x4);
pub const BORF0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const EXTRF: RegisterBits<Self> = RegisterBits::new(0x2);
pub const EXTRF0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const PORF: RegisterBits<Self> = RegisterBits::new(0x1);
pub const PORF0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for MCUSR {
type T = u8;
const ADDRESS: *mut u8 = 0x34 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct OSCCAL;
impl OSCCAL {
pub const OSCCAL: RegisterBits<Self> = RegisterBits::new(0xff);
pub const OSCCAL0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const OSCCAL1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const OSCCAL2: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const OSCCAL3: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const OSCCAL4: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const OSCCAL5: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const OSCCAL6: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const OSCCAL7: RegisterBits<Self> = RegisterBits::new(1<<7);
}
impl Register for OSCCAL {
type T = u8;
const ADDRESS: *mut u8 = 0x31 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct GIMSK;
impl GIMSK {
pub const INT0: RegisterBits<Self> = RegisterBits::new(0x40);
pub const INT00: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const PCIE: RegisterBits<Self> = RegisterBits::new(0x20);
pub const PCIE0: RegisterBits<Self> = RegisterBits::new(1<<5);
}
impl Register for GIMSK {
type T = u8;
const ADDRESS: *mut u8 = 0x3b as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct GIFR;
impl GIFR {
pub const INTF0: RegisterBits<Self> = RegisterBits::new(0x40);
pub const INTF00: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const PCIF: RegisterBits<Self> = RegisterBits::new(0x20);
pub const PCIF0: RegisterBits<Self> = RegisterBits::new(1<<5);
}
impl Register for GIFR {
type T = u8;
const ADDRESS: *mut u8 = 0x3a as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct EEAR;
impl EEAR {
}
impl Register for EEAR {
type T = u8;
const ADDRESS: *mut u8 = 0x1e as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct EEDR;
impl EEDR {
}
impl Register for EEDR {
type T = u8;
const ADDRESS: *mut u8 = 0x1d as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct EECR;
impl EECR {
pub const EERIE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const EERIE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const EEMWE: RegisterBits<Self> = RegisterBits::new(0x4);
pub const EEMWE0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const EEWE: RegisterBits<Self> = RegisterBits::new(0x2);
pub const EEWE0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const EERE: RegisterBits<Self> = RegisterBits::new(0x1);
pub const EERE0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for EECR {
type T = u8;
const ADDRESS: *mut u8 = 0x1c as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PORTB;
impl PORTB {
}
impl Register for PORTB {
type T = u8;
const ADDRESS: *mut u8 = 0x18 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct DDRB;
impl DDRB {
}
impl Register for DDRB {
type T = u8;
const ADDRESS: *mut u8 = 0x17 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PINB;
impl PINB {
}
impl Register for PINB {
type T = u8;
const ADDRESS: *mut u8 = 0x16 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TIMSK;
impl TIMSK {
pub const TOIE0: RegisterBits<Self> = RegisterBits::new(0x2);
pub const TOIE00: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for TIMSK {
type T = u8;
const ADDRESS: *mut u8 = 0x39 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TIFR;
impl TIFR {
pub const TOV0: RegisterBits<Self> = RegisterBits::new(0x2);
pub const TOV00: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for TIFR {
type T = u8;
const ADDRESS: *mut u8 = 0x38 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCCR0;
impl TCCR0 {
pub const CS02: RegisterBits<Self> = RegisterBits::new(0x4);
pub const CS020: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const CS01: RegisterBits<Self> = RegisterBits::new(0x2);
pub const CS010: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const CS00: RegisterBits<Self> = RegisterBits::new(0x1);
pub const CS000: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for TCCR0 {
type T = u8;
const ADDRESS: *mut u8 = 0x33 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCNT0;
impl TCNT0 {
}
impl Register for TCNT0 {
type T = u8;
const ADDRESS: *mut u8 = 0x32 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct WDTCR;
impl WDTCR {
pub const WDTOE: RegisterBits<Self> = RegisterBits::new(0x10);
pub const WDTOE0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const WDE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const WDE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const WDP: RegisterBits<Self> = RegisterBits::new(0x7);
pub const WDP0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const WDP1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const WDP2: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for WDTCR {
type T = u8;
const ADDRESS: *mut u8 = 0x21 as *mut u8;
}
pub mod port {
#![allow(unused_imports)]
use super::*;
use crate::Pin;
}

1746
src/cores/attiny1634.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1342
src/cores/attiny20.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1038
src/cores/attiny2313.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1111
src/cores/attiny2313a.rs Normal file
View File

File diff suppressed because it is too large Load Diff

726
src/cores/attiny26.rs Normal file
View File

@ -0,0 +1,726 @@
//! Core for ATtiny26.
use crate::{modules, RegisterBits, Register};
#[allow(non_camel_case_types)]
pub struct HIGH;
impl HIGH {
pub const RSTDISBL: RegisterBits<Self> = RegisterBits::new(0x10);
pub const RSTDISBL0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const SPIEN: RegisterBits<Self> = RegisterBits::new(0x8);
pub const SPIEN0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const EESAVE: RegisterBits<Self> = RegisterBits::new(0x4);
pub const EESAVE0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const BODLEVEL: RegisterBits<Self> = RegisterBits::new(0x2);
pub const BODLEVEL0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const BODEN: RegisterBits<Self> = RegisterBits::new(0x1);
pub const BODEN0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for HIGH {
type T = u8;
const ADDRESS: *mut u8 = 0x1 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct LOW;
impl LOW {
pub const CKOPT: RegisterBits<Self> = RegisterBits::new(0x40);
pub const CKOPT0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const PLLCK_SUT_CKSEL: RegisterBits<Self> = RegisterBits::new(0xbf);
pub const PLLCK_SUT_CKSEL0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const PLLCK_SUT_CKSEL1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const PLLCK_SUT_CKSEL2: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const PLLCK_SUT_CKSEL3: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const PLLCK_SUT_CKSEL4: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const PLLCK_SUT_CKSEL5: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const PLLCK_SUT_CKSEL6: RegisterBits<Self> = RegisterBits::new(1<<7);
}
impl Register for LOW {
type T = u8;
const ADDRESS: *mut u8 = 0x0 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct LOCKBIT;
impl LOCKBIT {
pub const LB: RegisterBits<Self> = RegisterBits::new(0x3);
pub const LB0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const LB1: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for LOCKBIT {
type T = u8;
const ADDRESS: *mut u8 = 0x0 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct ADMUX;
impl ADMUX {
pub const REFS: RegisterBits<Self> = RegisterBits::new(0xc0);
pub const REFS0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const REFS1: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const ADLAR: RegisterBits<Self> = RegisterBits::new(0x20);
pub const ADLAR0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const MUX: RegisterBits<Self> = RegisterBits::new(0x1f);
pub const MUX0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const MUX1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const MUX2: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const MUX3: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const MUX4: RegisterBits<Self> = RegisterBits::new(1<<4);
}
impl Register for ADMUX {
type T = u8;
const ADDRESS: *mut u8 = 0x27 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct ADCSR;
impl ADCSR {
pub const ADEN: RegisterBits<Self> = RegisterBits::new(0x80);
pub const ADEN0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const ADSC: RegisterBits<Self> = RegisterBits::new(0x40);
pub const ADSC0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const ADFR: RegisterBits<Self> = RegisterBits::new(0x20);
pub const ADFR0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const ADIF: RegisterBits<Self> = RegisterBits::new(0x10);
pub const ADIF0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const ADIE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const ADIE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const ADPS: RegisterBits<Self> = RegisterBits::new(0x7);
pub const ADPS0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const ADPS1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const ADPS2: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for ADCSR {
type T = u8;
const ADDRESS: *mut u8 = 0x26 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct ADC;
impl ADC {
}
impl Register for ADC {
type T = u16;
const ADDRESS: *mut u16 = 0x24 as *mut u16;
}
#[allow(non_camel_case_types)]
pub struct ACSR;
impl ACSR {
pub const ACD: RegisterBits<Self> = RegisterBits::new(0x80);
pub const ACD0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const ACBG: RegisterBits<Self> = RegisterBits::new(0x40);
pub const ACBG0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const ACO: RegisterBits<Self> = RegisterBits::new(0x20);
pub const ACO0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const ACI: RegisterBits<Self> = RegisterBits::new(0x10);
pub const ACI0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const ACIE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const ACIE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const ACME: RegisterBits<Self> = RegisterBits::new(0x4);
pub const ACME0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const ACIS: RegisterBits<Self> = RegisterBits::new(0x3);
pub const ACIS0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const ACIS1: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for ACSR {
type T = u8;
const ADDRESS: *mut u8 = 0x28 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct USIDR;
impl USIDR {
}
impl Register for USIDR {
type T = u8;
const ADDRESS: *mut u8 = 0x2f as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct USISR;
impl USISR {
pub const USISIF: RegisterBits<Self> = RegisterBits::new(0x80);
pub const USISIF0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const USIOIF: RegisterBits<Self> = RegisterBits::new(0x40);
pub const USIOIF0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const USIPF: RegisterBits<Self> = RegisterBits::new(0x20);
pub const USIPF0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const USIDC: RegisterBits<Self> = RegisterBits::new(0x10);
pub const USIDC0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const USICNT: RegisterBits<Self> = RegisterBits::new(0xf);
pub const USICNT0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const USICNT1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const USICNT2: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const USICNT3: RegisterBits<Self> = RegisterBits::new(1<<3);
}
impl Register for USISR {
type T = u8;
const ADDRESS: *mut u8 = 0x2e as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct USICR;
impl USICR {
pub const USISIE: RegisterBits<Self> = RegisterBits::new(0x80);
pub const USISIE0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const USIOIE: RegisterBits<Self> = RegisterBits::new(0x40);
pub const USIOIE0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const USIWM: RegisterBits<Self> = RegisterBits::new(0x30);
pub const USIWM0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const USIWM1: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const USICS: RegisterBits<Self> = RegisterBits::new(0xc);
pub const USICS0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const USICS1: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const USICLK: RegisterBits<Self> = RegisterBits::new(0x2);
pub const USICLK0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const USITC: RegisterBits<Self> = RegisterBits::new(0x1);
pub const USITC0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for USICR {
type T = u8;
const ADDRESS: *mut u8 = 0x2d as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PORTA;
impl PORTA {
}
impl Register for PORTA {
type T = u8;
const ADDRESS: *mut u8 = 0x3b as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct DDRA;
impl DDRA {
}
impl Register for DDRA {
type T = u8;
const ADDRESS: *mut u8 = 0x3a as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PINA;
impl PINA {
}
impl Register for PINA {
type T = u8;
const ADDRESS: *mut u8 = 0x39 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PORTB;
impl PORTB {
}
impl Register for PORTB {
type T = u8;
const ADDRESS: *mut u8 = 0x38 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct DDRB;
impl DDRB {
}
impl Register for DDRB {
type T = u8;
const ADDRESS: *mut u8 = 0x37 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PINB;
impl PINB {
}
impl Register for PINB {
type T = u8;
const ADDRESS: *mut u8 = 0x36 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct EEAR;
impl EEAR {
}
impl Register for EEAR {
type T = u8;
const ADDRESS: *mut u8 = 0x3e as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct EEDR;
impl EEDR {
}
impl Register for EEDR {
type T = u8;
const ADDRESS: *mut u8 = 0x3d as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct EECR;
impl EECR {
pub const EERIE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const EERIE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const EEMWE: RegisterBits<Self> = RegisterBits::new(0x4);
pub const EEMWE0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const EEWE: RegisterBits<Self> = RegisterBits::new(0x2);
pub const EEWE0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const EERE: RegisterBits<Self> = RegisterBits::new(0x1);
pub const EERE0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for EECR {
type T = u8;
const ADDRESS: *mut u8 = 0x3c as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct WDTCR;
impl WDTCR {
pub const WDCE: RegisterBits<Self> = RegisterBits::new(0x10);
pub const WDCE0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const WDE: RegisterBits<Self> = RegisterBits::new(0x8);
pub const WDE0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const WDP: RegisterBits<Self> = RegisterBits::new(0x7);
pub const WDP0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const WDP1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const WDP2: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for WDTCR {
type T = u8;
const ADDRESS: *mut u8 = 0x41 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct SREG;
impl SREG {
pub const I: RegisterBits<Self> = RegisterBits::new(0x80);
pub const I0: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const T: RegisterBits<Self> = RegisterBits::new(0x40);
pub const T0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const H: RegisterBits<Self> = RegisterBits::new(0x20);
pub const H0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const S: RegisterBits<Self> = RegisterBits::new(0x10);
pub const S0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const V: RegisterBits<Self> = RegisterBits::new(0x8);
pub const V0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const N: RegisterBits<Self> = RegisterBits::new(0x4);
pub const N0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const Z: RegisterBits<Self> = RegisterBits::new(0x2);
pub const Z0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const C: RegisterBits<Self> = RegisterBits::new(0x1);
pub const C0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for SREG {
type T = u8;
const ADDRESS: *mut u8 = 0x5f as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct SP;
impl SP {
}
impl Register for SP {
type T = u8;
const ADDRESS: *mut u8 = 0x5d as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct MCUCR;
impl MCUCR {
pub const PUD: RegisterBits<Self> = RegisterBits::new(0x40);
pub const PUD0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const SE: RegisterBits<Self> = RegisterBits::new(0x20);
pub const SE0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const SM: RegisterBits<Self> = RegisterBits::new(0x18);
pub const SM0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const SM1: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const ISC0: RegisterBits<Self> = RegisterBits::new(0x3);
pub const ISC00: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const ISC01: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for MCUCR {
type T = u8;
const ADDRESS: *mut u8 = 0x55 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct MCUSR;
impl MCUSR {
pub const WDRF: RegisterBits<Self> = RegisterBits::new(0x8);
pub const WDRF0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const BORF: RegisterBits<Self> = RegisterBits::new(0x4);
pub const BORF0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const EXTRF: RegisterBits<Self> = RegisterBits::new(0x2);
pub const EXTRF0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const PORF: RegisterBits<Self> = RegisterBits::new(0x1);
pub const PORF0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for MCUSR {
type T = u8;
const ADDRESS: *mut u8 = 0x54 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct OSCCAL;
impl OSCCAL {
pub const OSCCAL: RegisterBits<Self> = RegisterBits::new(0xff);
pub const OSCCAL0: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const OSCCAL1: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const OSCCAL2: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const OSCCAL3: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const OSCCAL4: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const OSCCAL5: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const OSCCAL6: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const OSCCAL7: RegisterBits<Self> = RegisterBits::new(1<<7);
}
impl Register for OSCCAL {
type T = u8;
const ADDRESS: *mut u8 = 0x51 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TIMSK;
impl TIMSK {
pub const TOIE0: RegisterBits<Self> = RegisterBits::new(0x2);
pub const TOIE00: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for TIMSK {
type T = u8;
const ADDRESS: *mut u8 = 0x59 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TIFR;
impl TIFR {
pub const TOV0: RegisterBits<Self> = RegisterBits::new(0x2);
pub const TOV00: RegisterBits<Self> = RegisterBits::new(1<<1);
}
impl Register for TIFR {
type T = u8;
const ADDRESS: *mut u8 = 0x58 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCCR0;
impl TCCR0 {
pub const PSR0: RegisterBits<Self> = RegisterBits::new(0x8);
pub const PSR00: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const CS0: RegisterBits<Self> = RegisterBits::new(0x7);
pub const CS00: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const CS01: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const CS02: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for TCCR0 {
type T = u8;
const ADDRESS: *mut u8 = 0x53 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCNT0;
impl TCNT0 {
}
impl Register for TCNT0 {
type T = u8;
const ADDRESS: *mut u8 = 0x52 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCCR1A;
impl TCCR1A {
pub const COM1A: RegisterBits<Self> = RegisterBits::new(0xc0);
pub const COM1A0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const COM1A1: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const COM1B: RegisterBits<Self> = RegisterBits::new(0x30);
pub const COM1B0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const COM1B1: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const FOC1A: RegisterBits<Self> = RegisterBits::new(0x8);
pub const FOC1A0: RegisterBits<Self> = RegisterBits::new(1<<3);
pub const FOC1B: RegisterBits<Self> = RegisterBits::new(0x4);
pub const FOC1B0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const PWM1A: RegisterBits<Self> = RegisterBits::new(0x2);
pub const PWM1A0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const PWM1B: RegisterBits<Self> = RegisterBits::new(0x1);
pub const PWM1B0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for TCCR1A {
type T = u8;
const ADDRESS: *mut u8 = 0x50 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCCR1B;
impl TCCR1B {
pub const CTC1: RegisterBits<Self> = RegisterBits::new(0x80);
pub const CTC10: RegisterBits<Self> = RegisterBits::new(1<<7);
pub const PSR1: RegisterBits<Self> = RegisterBits::new(0x40);
pub const PSR10: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const CS1: RegisterBits<Self> = RegisterBits::new(0xf);
pub const CS10: RegisterBits<Self> = RegisterBits::new(1<<0);
pub const CS11: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const CS12: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const CS13: RegisterBits<Self> = RegisterBits::new(1<<3);
}
impl Register for TCCR1B {
type T = u8;
const ADDRESS: *mut u8 = 0x4f as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TCNT1;
impl TCNT1 {
}
impl Register for TCNT1 {
type T = u8;
const ADDRESS: *mut u8 = 0x4e as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct OCR1A;
impl OCR1A {
}
impl Register for OCR1A {
type T = u8;
const ADDRESS: *mut u8 = 0x4d as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct OCR1B;
impl OCR1B {
}
impl Register for OCR1B {
type T = u8;
const ADDRESS: *mut u8 = 0x4c as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct OCR1C;
impl OCR1C {
}
impl Register for OCR1C {
type T = u8;
const ADDRESS: *mut u8 = 0x4b as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TIMSK;
impl TIMSK {
pub const OCIE1A: RegisterBits<Self> = RegisterBits::new(0x40);
pub const OCIE1A0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const OCIE1B: RegisterBits<Self> = RegisterBits::new(0x20);
pub const OCIE1B0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const TOIE1: RegisterBits<Self> = RegisterBits::new(0x4);
pub const TOIE10: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for TIMSK {
type T = u8;
const ADDRESS: *mut u8 = 0x59 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct TIFR;
impl TIFR {
pub const OCF1A: RegisterBits<Self> = RegisterBits::new(0x40);
pub const OCF1A0: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const OCF1B: RegisterBits<Self> = RegisterBits::new(0x20);
pub const OCF1B0: RegisterBits<Self> = RegisterBits::new(1<<5);
pub const TOV1: RegisterBits<Self> = RegisterBits::new(0x4);
pub const TOV10: RegisterBits<Self> = RegisterBits::new(1<<2);
}
impl Register for TIFR {
type T = u8;
const ADDRESS: *mut u8 = 0x58 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct PLLCSR;
impl PLLCSR {
pub const PCKE: RegisterBits<Self> = RegisterBits::new(0x4);
pub const PCKE0: RegisterBits<Self> = RegisterBits::new(1<<2);
pub const PLLE: RegisterBits<Self> = RegisterBits::new(0x2);
pub const PLLE0: RegisterBits<Self> = RegisterBits::new(1<<1);
pub const PLOCK: RegisterBits<Self> = RegisterBits::new(0x1);
pub const PLOCK0: RegisterBits<Self> = RegisterBits::new(1<<0);
}
impl Register for PLLCSR {
type T = u8;
const ADDRESS: *mut u8 = 0x49 as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct GIMSK;
impl GIMSK {
pub const INT0: RegisterBits<Self> = RegisterBits::new(0x40);
pub const INT00: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const PCIE: RegisterBits<Self> = RegisterBits::new(0x30);
pub const PCIE0: RegisterBits<Self> = RegisterBits::new(1<<4);
pub const PCIE1: RegisterBits<Self> = RegisterBits::new(1<<5);
}
impl Register for GIMSK {
type T = u8;
const ADDRESS: *mut u8 = 0x5b as *mut u8;
}
#[allow(non_camel_case_types)]
pub struct GIFR;
impl GIFR {
pub const INTF0: RegisterBits<Self> = RegisterBits::new(0x40);
pub const INTF00: RegisterBits<Self> = RegisterBits::new(1<<6);
pub const PCIF: RegisterBits<Self> = RegisterBits::new(0x20);
pub const PCIF0: RegisterBits<Self> = RegisterBits::new(1<<5);
}
impl Register for GIFR {
type T = u8;
const ADDRESS: *mut u8 = 0x5a as *mut u8;
}
pub mod port {
#![allow(unused_imports)]
use super::*;
use crate::Pin;
}
/// 8-bit timer.
pub struct Timer8;
impl modules::Timer8 for Timer8 {
type CompareA = OCR1A;
type CompareB = OCR1B;
type Counter = TCNT1;
type ControlA = TCCR1A;
type ControlB = TCCR1B;
type InterruptMask = TIMSK;
type InterruptFlag = TIFR;
const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS00;
const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS01;
const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS02;
const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM00;
const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM01;
const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM020;
const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE1A;
}

1468
src/cores/attiny261.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1269
src/cores/attiny261a.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1461
src/cores/attiny40.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1111
src/cores/attiny4313.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1468
src/cores/attiny461.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1269
src/cores/attiny461a.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1115
src/cores/attiny85.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1470
src/cores/attiny861.rs Normal file
View File

File diff suppressed because it is too large Load Diff

1271
src/cores/attiny861a.rs Normal file
View File

File diff suppressed because it is too large Load Diff

60
src/cores/mod.rs
View File

@ -1,61 +1,7 @@
//! The primary module containing microcontroller-specific core definitions
/// The ATmega88.
#[cfg(any(avr_mcu_atmega88, feature = "all-mcus"))] pub mod atmega88;
#[cfg(avr_mcu_atmega88)] pub use self::atmega88 as current;
/// The ATmega48A.
#[cfg(any(avr_mcu_atmega48a, feature = "all-mcus"))] pub mod atmega48a;
#[cfg(avr_mcu_atmega48a)] pub use self::atmega48a as current;
/// The ATmega168A.
#[cfg(any(avr_mcu_atmega168a, feature = "all-mcus"))] pub mod atmega168a;
#[cfg(avr_mcu_atmega168a)] pub use self::atmega168a as current;
/// The ATmega88P.
#[cfg(any(avr_mcu_atmega88p, feature = "all-mcus"))] pub mod atmega88p;
#[cfg(avr_mcu_atmega88p)] pub use self::atmega88p as current;
/// The ATmega168P.
#[cfg(any(avr_mcu_atmega168p, feature = "all-mcus"))] pub mod atmega168p;
#[cfg(avr_mcu_atmega168p)] pub use self::atmega168p as current;
/// The ATmega88PA.
#[cfg(any(avr_mcu_atmega88pa, feature = "all-mcus"))] pub mod atmega88pa;
#[cfg(avr_mcu_atmega88pa)] pub use self::atmega88pa as current;
/// The ATmega168.
#[cfg(any(avr_mcu_atmega168, feature = "all-mcus"))] pub mod atmega168;
#[cfg(avr_mcu_atmega168)] pub use self::atmega168 as current;
/// The ATmega328P.
#[cfg(any(avr_mcu_atmega328p, feature = "all-mcus"))] pub mod atmega328p;
#[cfg(avr_mcu_atmega328p)] pub use self::atmega328p as current;
/// The ATmega48PA.
#[cfg(any(avr_mcu_atmega48pa, feature = "all-mcus"))] pub mod atmega48pa;
#[cfg(avr_mcu_atmega48pa)] pub use self::atmega48pa as current;
/// The ATmega168PA.
#[cfg(any(avr_mcu_atmega168pa, feature = "all-mcus"))] pub mod atmega168pa;
#[cfg(avr_mcu_atmega168pa)] pub use self::atmega168pa as current;
/// The ATmega48P.
#[cfg(any(avr_mcu_atmega48p, feature = "all-mcus"))] pub mod atmega48p;
#[cfg(avr_mcu_atmega48p)] pub use self::atmega48p as current;
/// The ATmega328.
///
/// This device is chosen as the default when the crate is targeting non-AVR devices.
#[cfg(any(avr_mcu_atmega328, feature = "all-mcus", not(target_arch = "avr")))] pub mod atmega328;
#[cfg(any(avr_mcu_atmega328, not(target_arch = "avr")))] pub use self::atmega328 as current;
/// The ATmega88A.
#[cfg(any(avr_mcu_atmega88a, feature = "all-mcus"))] pub mod atmega88a;
#[cfg(avr_mcu_atmega88a)] pub use self::atmega88a as current;
/// The ATmega48.
#[cfg(any(avr_mcu_atmega48, feature = "all-mcus"))] pub mod atmega48;
#[cfg(avr_mcu_atmega48)] pub use self::atmega48 as current;
/// The ATtiny85.
#[cfg(any(avr_mcu_attiny85, feature = "all-mcus"))] pub mod attiny85;
#[cfg(avr_mcu_attiny85)] pub use self::attiny85 as current;

35
src/modules/spi/mod.rs
View File

@ -1,34 +1,38 @@
mod clock;
// FIXME: Start using this module or delete!!!
#[allow(dead_code)] mod settings;
#[allow(dead_code)]
mod settings;
use crate::{Register, Pin};
use crate::{Pin, Register};
/// An SPI module.
///
/// Information at [maxembedded.com](http://maxembedded.com/2013/11/the-spi-of-the-avr/).
pub trait HardwareSpi {
type MasterInSlaveOut: Pin;
type MasterOutSlaveIn: Pin;
type SerialDataIn: Pin;
<<<<<<< Updated upstream
type SerialDataOu: Pin;
=======
type SerialDataOut: Pin;
>>>>>>> Stashed changes
type Clock: Pin;
type SlaveSelect: Pin;
type ChipSelect: Pin;
/// The SPI control register.
type ControlRegister: Register<T=u8>;
type ControlRegister: Register<T = u8>;
/// The SPI status register.
type StatusRegister: Register<T=u8>;
type StatusRegister: Register<T = u8>;
/// The SPI data register.
type DataRegister: Register<T=u8>;
type DataRegister: Register<T = u8>;
/// Sets up the SPI as a master.
fn setup_master(clock: u32) {
// Setup DDR registers.
Self::MasterInSlaveOut::set_input();
Self::MasterOutSlaveIn::set_output();
Self::SerialDataIn::set_input();
Self::SerialDataOut::set_output();
Self::Clock::set_output();
Self::SlaveSelect::set_input();
Self::ChipSelect::set_input();
Self::set_master();
Self::enable_interrupt();
@ -38,10 +42,10 @@ pub trait HardwareSpi {
/// Sets up the SPI as a slave.
fn setup_slave(clock: u32) {
// Setup DDR registers.
Self::MasterInSlaveOut::set_output();
Self::MasterOutSlaveIn::set_input();
Self::SerialDataIn::set_output();
Self::SerialDataOut::set_input();
Self::Clock::set_input();
Self::SlaveSelect::set_input();
Self::ChipSelect::set_input();
Self::set_slave();
Self::setup_common(clock)
@ -147,4 +151,3 @@ pub trait HardwareSpi {
Self::DataRegister::read()
}
}