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expanded-s
Author | SHA1 | Date |
---|---|---|
Savanni D'Gerinel | 8235d34f95 | |
Savanni D'Gerinel | f516e1216b |
|
@ -1,13 +1,17 @@
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use avr_mcu::*;
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use std::io;
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use std::io::prelude::*;
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use std::{
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collections::HashMap,
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io::{self, prelude::*},
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};
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pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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for register in mcu.registers() {
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let ty = if register.size == 1 { "u8" } else { "u16" };
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// HACK: Skip, atmeg328p pack defines two of these.
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if register.name == "GTCCR" { continue; }
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if register.name == "GTCCR" {
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continue;
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}
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writeln!(w, "#[allow(non_camel_case_types)]")?;
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writeln!(w, "pub struct {};", register.name)?;
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@ -16,7 +20,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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writeln!(w, "impl {} {{", register.name)?;
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for bitfield in register.bitfields.iter() {
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// Create a mask for the whole bitset.
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writeln!(w, " pub const {}: RegisterBits<Self> = RegisterBits::new(0x{:x});", bitfield.name, bitfield.mask)?;
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writeln!(
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w,
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" pub const {}: RegisterBits<Self> = RegisterBits::new(0x{:x});",
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bitfield.name, bitfield.mask
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)?;
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// We create masks for the individual bits in the field if there
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// is more than one bit in the field.
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@ -24,8 +32,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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let mut current_mask_bit_num = 0;
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for current_register_bit_num in 0..15 {
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if (current_mask & 0b1) == 0b1 {
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writeln!(w, " pub const {}{}: RegisterBits<Self> = RegisterBits::new(1<<{});",
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bitfield.name, current_mask_bit_num, current_register_bit_num)?;
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writeln!(
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w,
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" pub const {}{}: RegisterBits<Self> = RegisterBits::new(1<<{});",
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bitfield.name, current_mask_bit_num, current_register_bit_num
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)?;
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current_mask_bit_num += 1;
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}
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@ -38,7 +49,11 @@ pub fn write_registers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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writeln!(w, "impl Register for {} {{", register.name)?;
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writeln!(w, " type T = {};", ty)?;
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writeln!(w, " const ADDRESS: *mut {} = 0x{:x} as *mut {};", ty, register.offset, ty)?;
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writeln!(
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w,
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" const ADDRESS: *mut {} = 0x{:x} as *mut {};",
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ty, register.offset, ty
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)?;
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writeln!(w, "}}")?;
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}
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@ -61,9 +76,14 @@ pub fn write_pins(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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let idx = signal.index.expect("signal with no index");
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let struct_name = format!("{}{}", port_letter, idx);
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let io_module = mcu.modules.iter().find(|m| m.name == "PORT")
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let io_module = mcu
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.modules
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.iter()
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.find(|m| m.name == "PORT")
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.expect("no port io module defined for this port");
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let register_group = io_module.register_groups.iter()
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let register_group = io_module
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.register_groups
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.iter()
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.find(|rg| rg.name == instance.name)
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.expect("no register group defined for this port");
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@ -90,30 +110,52 @@ pub fn write_pins(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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Ok(())
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}
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#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
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enum SpiPinType {
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SerialDataIn,
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SerialDataOut,
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Clock,
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ChipSelect,
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}
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pub fn write_spi_modules(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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if let Some(module) = mcu.module("SPI") {
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let peripheral = mcu.peripheral("SPI").expect("found SPI module but no peripheral");
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let peripheral = mcu
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.peripheral("SPI")
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.expect("found SPI module but no peripheral");
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let port_peripheral = mcu.port_peripheral();
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writeln!(w, "pub struct Spi;")?;
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writeln!(w)?;
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writeln!(w, "impl modules::HardwareSpi for Spi {{")?;
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let mut pins: HashMap<SpiPinType, String> = HashMap::new();
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for spi_signal in peripheral.signals() {
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let spi_signal_name = spi_signal.group.clone().expect("spi signal does not have group name");
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let (port_instance, port_signal) = port_peripheral.instance_signal_with_pad(&spi_signal.pad)
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let spi_signal_name = spi_signal
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.group
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.clone()
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.expect("spi signal does not have group name");
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let (port_instance, port_signal) = port_peripheral
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.instance_signal_with_pad(&spi_signal.pad)
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.expect("no port signal associated with the spi signal pad");
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let pin_name = self::pin_name(port_instance, port_signal);
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let const_name = match &spi_signal_name[..] {
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"MISO" => "MasterInSlaveOut",
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"MOSI" => "MasterOutSlaveIn",
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"SCK" => "Clock",
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"SS" => "SlaveSelect",
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"MISO" => SpiPinType::SerialDataIn,
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"MOSI" => SpiPinType::SerialDataOut,
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"SCK" => SpiPinType::Clock,
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"SS" => SpiPinType::ChipSelect,
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"CS" => SpiPinType::ChipSelect,
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"PDI" => SpiPinType::SerialDataOut,
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"PDO" => SpiPinType::SerialDataIn,
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_ => panic!("unknown spi signal name: '{}'", spi_signal_name),
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};
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writeln!(w, " type {} = {};", const_name, pin_name)?;
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pins.insert(const_name, pin_name);
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}
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for (pin_type, pin_name) in pins.into_iter() {
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writeln!(w, " type {:?} = {};", pin_type, pin_name)?;
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}
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for reg in module.registers() {
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@ -140,12 +182,15 @@ pub fn write_usarts(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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writeln!(w)?;
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writeln!(w, "impl modules::HardwareUsart for {} {{", usart.name)?;
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for register in usart.registers.iter() {
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let reg_ty = if register.name.starts_with("UDR") { // the data register.
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let reg_ty = if register.name.starts_with("UDR") {
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// the data register.
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"DataRegister".to_owned()
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} else if register.name.starts_with("UCSR") { // one of the three control/status registers.
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} else if register.name.starts_with("UCSR") {
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// one of the three control/status registers.
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let suffix = register.name.chars().rev().next().unwrap();
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format!("ControlRegister{}", suffix)
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} else if register.name.starts_with("UBRR") { // the baud rate register.
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} else if register.name.starts_with("UBRR") {
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// the baud rate register.
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"BaudRateRegister".to_owned()
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} else {
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panic!("unknown usart register '{}'", register.name);
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@ -160,22 +205,30 @@ pub fn write_usarts(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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}
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pub fn write_timers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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if let Some(tc) = mcu.module("TC8") { // Timer/Counter, 8-bit.
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if let Some(tc) = mcu.module("TC8") {
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// Timer/Counter, 8-bit.
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const TYPE_NAME: &'static str = "Timer8";
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let find_reg = |name: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name))
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tc.registers()
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.find(|r| r.name.starts_with(name))
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.expect(&format!("could not find '{}' register", name))
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};
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let find_reg_suffix_optional = |name: &'static str, suffix: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
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tc.registers()
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.find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
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};
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let find_reg_suffix = |name: &'static str, suffix: &'static str| {
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find_reg_suffix_optional(name, suffix)
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.expect(&format!("could not find '{}' register", name))
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};
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let timer_number = find_reg("TIMSK").name.chars().last().unwrap()
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.to_digit(10).unwrap();
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let timer_number = find_reg("TIMSK")
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.name
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.chars()
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.last()
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.unwrap()
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.to_digit(10)
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.unwrap();
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// TODO: At the moment, we do not support 8 bit timers that don't have two compare
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// registers.
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@ -186,58 +239,145 @@ pub fn write_timers(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
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writeln!(w, "pub struct {};", TYPE_NAME)?;
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writeln!(w)?;
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writeln!(w, "impl modules::Timer8 for {} {{", TYPE_NAME)?;
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writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
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writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
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writeln!(
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w,
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" type CompareA = {};",
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find_reg_suffix("OCR", "A").name
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)?;
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writeln!(
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w,
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" type CompareB = {};",
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find_reg_suffix("OCR", "B").name
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)?;
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writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
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writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
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writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
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writeln!(
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w,
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" type ControlA = {};",
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find_reg_suffix("TCCR", "A").name
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)?;
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writeln!(
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w,
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" type ControlB = {};",
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find_reg_suffix("TCCR", "B").name
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)?;
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writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
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writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
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writeln!(w, " const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS00;")?;
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writeln!(w, " const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS01;")?;
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writeln!(w, " const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS02;")?;
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writeln!(w, " const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM00;")?;
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writeln!(w, " const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM01;")?;
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writeln!(w, " const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM020;")?;
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writeln!(
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w,
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" const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS00;"
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)?;
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writeln!(
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w,
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" const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS01;"
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)?;
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writeln!(
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w,
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" const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS02;"
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)?;
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writeln!(
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w,
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" const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM00;"
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)?;
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writeln!(
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w,
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" const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM01;"
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)?;
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writeln!(
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w,
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" const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM020;"
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)?;
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writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
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writeln!(w, "}}")?;
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}
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}
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if let Some(tc) = mcu.module("TC16") { // Timer/Counter, 16-bit.
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if let Some(tc) = mcu.module("TC16") {
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// Timer/Counter, 16-bit.
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const TYPE_NAME: &'static str = "Timer16";
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let find_reg = |name: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name))
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tc.registers()
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.find(|r| r.name.starts_with(name))
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.expect(&format!("could not find '{}' register", name))
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};
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let find_reg_suffix = |name: &'static str, suffix: &'static str| {
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tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
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tc.registers()
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.find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
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.expect(&format!("could not find '{}' register", name))
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};
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let timer_number = find_reg("TIMSK").name.chars().last().unwrap()
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.to_digit(10).unwrap();
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let timer_number = find_reg("TIMSK")
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.name
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.chars()
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.last()
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.unwrap()
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.to_digit(10)
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.unwrap();
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writeln!(w, "/// 16-bit timer.")?;
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writeln!(w, "pub struct {};", TYPE_NAME)?;
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writeln!(w)?;
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writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?;
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writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
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writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
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writeln!(
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w,
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" type CompareA = {};",
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find_reg_suffix("OCR", "A").name
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)?;
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writeln!(
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w,
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" type CompareB = {};",
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find_reg_suffix("OCR", "B").name
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)?;
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writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
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writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
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writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
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writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?;
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writeln!(
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w,
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" type ControlA = {};",
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find_reg_suffix("TCCR", "A").name
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)?;
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writeln!(
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w,
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" type ControlB = {};",
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find_reg_suffix("TCCR", "B").name
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)?;
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writeln!(
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w,
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" type ControlC = {};",
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find_reg_suffix("TCCR", "C").name
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)?;
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writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
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writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
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writeln!(w, " const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS10;")?;
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writeln!(w, " const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS11;")?;
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writeln!(w, " const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS12;")?;
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writeln!(w, " const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM10;")?;
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writeln!(w, " const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM11;")?;
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writeln!(w, " const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM10;")?;
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writeln!(w, " const WGM3: RegisterBits<Self::ControlB> = Self::ControlB::WGM11;")?;
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writeln!(w, " const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;", timer_number)?;
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writeln!(
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w,
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" const CS0: RegisterBits<Self::ControlB> = Self::ControlB::CS10;"
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)?;
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writeln!(
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w,
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" const CS1: RegisterBits<Self::ControlB> = Self::ControlB::CS11;"
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)?;
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writeln!(
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w,
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" const CS2: RegisterBits<Self::ControlB> = Self::ControlB::CS12;"
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)?;
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writeln!(
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w,
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" const WGM0: RegisterBits<Self::ControlA> = Self::ControlA::WGM10;"
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)?;
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writeln!(
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w,
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" const WGM1: RegisterBits<Self::ControlA> = Self::ControlA::WGM11;"
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)?;
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writeln!(
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w,
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" const WGM2: RegisterBits<Self::ControlB> = Self::ControlB::WGM10;"
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)?;
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writeln!(
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w,
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" const WGM3: RegisterBits<Self::ControlB> = Self::ControlB::WGM11;"
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)?;
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writeln!(
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w,
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" const OCIEA: RegisterBits<Self::InterruptMask> = Self::InterruptMask::OCIE{}A;",
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timer_number
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)?;
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writeln!(w, "}}")?;
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}
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|
|
|
@ -116,7 +116,9 @@ const DISABLE_FOR_DEVICES: &'static [&'static str] = &[
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fn base_output_path() -> PathBuf {
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match std::env::args().skip(1).next() {
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Some(path) => Path::new(&path).to_owned(),
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None => panic!("please pass a destination path for the generated cores on the command line"),
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None => {
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panic!("please pass a destination path for the generated cores on the command line")
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}
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}
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}
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|
@ -137,17 +139,27 @@ fn main() {
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fs::create_dir_all(&cores_path()).expect("could not create cores directory");
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}
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// let microcontrollers = vec![avr_mcu::microcontroller("atmega32u4")];
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let microcontrollers = avr_mcu::microcontrollers();
|
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let (count_total, mut cores_successful, mut cores_failed) = (microcontrollers.len(), Vec::new(), Vec::new());
|
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let (count_total, mut cores_successful, mut cores_failed) =
|
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(microcontrollers.len(), Vec::new(), Vec::new());
|
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|
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for (i, mcu) in microcontrollers.iter().enumerate() {
|
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if DISABLE_FOR_DEVICES.iter().any(|d| mcu.device.name == *d || core_module_name(mcu) == *d) {
|
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if DISABLE_FOR_DEVICES
|
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.iter()
|
||||
.any(|d| mcu.device.name == *d || core_module_name(mcu) == *d)
|
||||
{
|
||||
println!("skipping generation of core for '{}'", mcu.device.name);
|
||||
continue;
|
||||
}
|
||||
|
||||
let result = std::panic::catch_unwind(|| {
|
||||
println!("generating core for '{}' ({} of {})", mcu.device.name, i + 1, count_total);
|
||||
println!(
|
||||
"generating core for '{}' ({} of {})",
|
||||
mcu.device.name,
|
||||
i + 1,
|
||||
count_total
|
||||
);
|
||||
generate_cores(&[mcu.clone()]).unwrap();
|
||||
});
|
||||
|
||||
|
@ -155,7 +167,7 @@ fn main() {
|
|||
Ok(..) => {
|
||||
println!("successfully generated core for '{}'", mcu.device.name);
|
||||
cores_successful.push(mcu);
|
||||
},
|
||||
}
|
||||
Err(e) => {
|
||||
delete_core_module(mcu).unwrap(); // Don't leave around broken core files.
|
||||
|
||||
|
@ -165,12 +177,18 @@ fn main() {
|
|||
String::new()
|
||||
};
|
||||
|
||||
eprintln!("failed to generate core for '{}', skipping: {}\n", mcu.device.name, error_message);
|
||||
eprintln!(
|
||||
"failed to generate core for '{}', skipping: {}\n",
|
||||
mcu.device.name, error_message
|
||||
);
|
||||
cores_failed.push(mcu);
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
println!("generating 'src/cores/mod.rs' for the {} successfully generated cores", cores_successful.len());
|
||||
println!(
|
||||
"generating 'src/cores/mod.rs' for the {} successfully generated cores",
|
||||
cores_successful.len()
|
||||
);
|
||||
generate_cores_mod_rs(&cores_successful[..]).expect("failed to generates src/cores/mod.rs");
|
||||
|
||||
println!("statistics:");
|
||||
|
@ -201,7 +219,10 @@ fn generate_cores_mod_rs(mcus: &[&Mcu]) -> Result<(), io::Error> {
|
|||
let path = cores_path().join("mod.rs");
|
||||
let mut w = File::create(&path)?;
|
||||
|
||||
writeln!(w, "//! The primary module containing microcontroller-specific core definitions")?;
|
||||
writeln!(
|
||||
w,
|
||||
"//! The primary module containing microcontroller-specific core definitions"
|
||||
)?;
|
||||
writeln!(w)?;
|
||||
|
||||
for mcu in mcus {
|
||||
|
@ -224,9 +245,17 @@ fn generate_cores_mod_rs(mcus: &[&Mcu]) -> Result<(), io::Error> {
|
|||
writeln!(w, "///\n/// This device is chosen as the default when the crate is targeting non-AVR devices.")?;
|
||||
}
|
||||
|
||||
writeln!(w, "#[cfg(any(avr_mcu_{}, feature = \"all-mcus\"{}))] pub mod {};", module_name, cfg_check_default_fallback, module_name)?;
|
||||
writeln!(
|
||||
w,
|
||||
"#[cfg(any(avr_mcu_{}, feature = \"all-mcus\"{}))] pub mod {};",
|
||||
module_name, cfg_check_default_fallback, module_name
|
||||
)?;
|
||||
|
||||
writeln!(w, "#[cfg({})] pub use self::{} as current;", current_module_check, module_name)?;
|
||||
writeln!(
|
||||
w,
|
||||
"#[cfg({})] pub use self::{} as current;",
|
||||
current_module_check, module_name
|
||||
)?;
|
||||
writeln!(w)?;
|
||||
}
|
||||
writeln!(w)
|
||||
|
@ -246,4 +275,3 @@ fn write_core_module(mcu: &Mcu, w: &mut dyn Write) -> Result<(), io::Error> {
|
|||
|
||||
writeln!(w)
|
||||
}
|
||||
|
||||
|
|
|
@ -1791,10 +1791,10 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type SerialDataIn = port::B4;
|
||||
type Clock = port::B5;
|
||||
type SerialDataOut = port::B3;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
type ControlRegister = SPCR;
|
||||
|
|
|
@ -1794,10 +1794,10 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type SerialDataOut = port::B3;
|
||||
type ChipSelect = port::B2;
|
||||
type Clock = port::B5;
|
||||
type SerialDataIn = port::B4;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
type ControlRegister = SPCR;
|
||||
|
|
|
@ -1800,9 +1800,9 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type SerialDataOut = port::B3;
|
||||
type SerialDataIn = port::B4;
|
||||
type Clock = port::B5;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
|
|
|
@ -1800,9 +1800,9 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type SerialDataOut = port::B3;
|
||||
type ChipSelect = port::B2;
|
||||
type SerialDataIn = port::B4;
|
||||
type Clock = port::B5;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -2040,10 +2040,10 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type Clock = port::B5;
|
||||
type SerialDataOut = port::B3;
|
||||
type ChipSelect = port::B2;
|
||||
type SerialDataIn = port::B4;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
type ControlRegister = SPCR;
|
||||
|
|
|
@ -1800,10 +1800,10 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type SerialDataOut = port::B3;
|
||||
type Clock = port::B5;
|
||||
type SerialDataIn = port::B4;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
type ControlRegister = SPCR;
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1773,10 +1773,10 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type SerialDataIn = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type Clock = port::B5;
|
||||
type SerialDataOut = port::B3;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
type ControlRegister = SPCR;
|
||||
|
|
|
@ -1798,9 +1798,9 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type SerialDataOut = port::B3;
|
||||
type SerialDataIn = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type Clock = port::B5;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
|
|
|
@ -1779,10 +1779,10 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type SerialDataIn = port::B4;
|
||||
type Clock = port::B5;
|
||||
type SerialDataOut = port::B3;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
type ControlRegister = SPCR;
|
||||
|
|
|
@ -1804,10 +1804,10 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type SerialDataOut = port::B3;
|
||||
type SerialDataIn = port::B4;
|
||||
type Clock = port::B5;
|
||||
type ChipSelect = port::B2;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
type ControlRegister = SPCR;
|
||||
|
|
|
@ -1791,9 +1791,9 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type SerialDataOut = port::B3;
|
||||
type SerialDataIn = port::B4;
|
||||
type Clock = port::B5;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
|
|
|
@ -1794,9 +1794,9 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type SerialDataOut = port::B3;
|
||||
type SerialDataIn = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type Clock = port::B5;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
|
|
|
@ -1797,10 +1797,10 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type Clock = port::B5;
|
||||
type SerialDataOut = port::B3;
|
||||
type SerialDataIn = port::B4;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
type ControlRegister = SPCR;
|
||||
|
|
|
@ -1800,9 +1800,9 @@ pub mod port {
|
|||
pub struct Spi;
|
||||
|
||||
impl modules::HardwareSpi for Spi {
|
||||
type SlaveSelect = port::B2;
|
||||
type MasterOutSlaveIn = port::B3;
|
||||
type MasterInSlaveOut = port::B4;
|
||||
type SerialDataOut = port::B3;
|
||||
type SerialDataIn = port::B4;
|
||||
type ChipSelect = port::B2;
|
||||
type Clock = port::B5;
|
||||
type DataRegister = SPDR;
|
||||
type StatusRegister = SPSR;
|
||||
|
|
|
@ -1,40 +1,50 @@
|
|||
//! The primary module containing microcontroller-specific core definitions
|
||||
|
||||
/// The ATmega88.
|
||||
#[cfg(any(avr_mcu_atmega88, feature = "all-mcus"))] pub mod atmega88;
|
||||
#[cfg(avr_mcu_atmega88)] pub use self::atmega88 as current;
|
||||
|
||||
/// The ATmega48A.
|
||||
#[cfg(any(avr_mcu_atmega48a, feature = "all-mcus"))] pub mod atmega48a;
|
||||
#[cfg(avr_mcu_atmega48a)] pub use self::atmega48a as current;
|
||||
|
||||
/// The ATmega168A.
|
||||
#[cfg(any(avr_mcu_atmega168a, feature = "all-mcus"))] pub mod atmega168a;
|
||||
#[cfg(avr_mcu_atmega168a)] pub use self::atmega168a as current;
|
||||
|
||||
/// The ATmega88P.
|
||||
#[cfg(any(avr_mcu_atmega88p, feature = "all-mcus"))] pub mod atmega88p;
|
||||
#[cfg(avr_mcu_atmega88p)] pub use self::atmega88p as current;
|
||||
|
||||
/// The ATmega168P.
|
||||
#[cfg(any(avr_mcu_atmega168p, feature = "all-mcus"))] pub mod atmega168p;
|
||||
#[cfg(avr_mcu_atmega168p)] pub use self::atmega168p as current;
|
||||
|
||||
/// The ATmega88PA.
|
||||
#[cfg(any(avr_mcu_atmega88pa, feature = "all-mcus"))] pub mod atmega88pa;
|
||||
#[cfg(avr_mcu_atmega88pa)] pub use self::atmega88pa as current;
|
||||
|
||||
/// The ATmega168.
|
||||
#[cfg(any(avr_mcu_atmega168, feature = "all-mcus"))] pub mod atmega168;
|
||||
#[cfg(avr_mcu_atmega168)] pub use self::atmega168 as current;
|
||||
/// The ATmega48PA.
|
||||
#[cfg(any(avr_mcu_atmega48pa, feature = "all-mcus"))] pub mod atmega48pa;
|
||||
#[cfg(avr_mcu_atmega48pa)] pub use self::atmega48pa as current;
|
||||
|
||||
/// The ATmega328P.
|
||||
#[cfg(any(avr_mcu_atmega328p, feature = "all-mcus"))] pub mod atmega328p;
|
||||
#[cfg(avr_mcu_atmega328p)] pub use self::atmega328p as current;
|
||||
|
||||
/// The ATmega48PA.
|
||||
#[cfg(any(avr_mcu_atmega48pa, feature = "all-mcus"))] pub mod atmega48pa;
|
||||
#[cfg(avr_mcu_atmega48pa)] pub use self::atmega48pa as current;
|
||||
/// The ATmega16U4.
|
||||
#[cfg(any(avr_mcu_atmega16u4, feature = "all-mcus"))] pub mod atmega16u4;
|
||||
#[cfg(avr_mcu_atmega16u4)] pub use self::atmega16u4 as current;
|
||||
|
||||
/// The ATmega88.
|
||||
#[cfg(any(avr_mcu_atmega88, feature = "all-mcus"))] pub mod atmega88;
|
||||
#[cfg(avr_mcu_atmega88)] pub use self::atmega88 as current;
|
||||
|
||||
/// The ATmega168A.
|
||||
#[cfg(any(avr_mcu_atmega168a, feature = "all-mcus"))] pub mod atmega168a;
|
||||
#[cfg(avr_mcu_atmega168a)] pub use self::atmega168a as current;
|
||||
|
||||
/// The ATmega48.
|
||||
#[cfg(any(avr_mcu_atmega48, feature = "all-mcus"))] pub mod atmega48;
|
||||
#[cfg(avr_mcu_atmega48)] pub use self::atmega48 as current;
|
||||
|
||||
/// The ATmega48A.
|
||||
#[cfg(any(avr_mcu_atmega48a, feature = "all-mcus"))] pub mod atmega48a;
|
||||
#[cfg(avr_mcu_atmega48a)] pub use self::atmega48a as current;
|
||||
|
||||
/// The ATmega88PA.
|
||||
#[cfg(any(avr_mcu_atmega88pa, feature = "all-mcus"))] pub mod atmega88pa;
|
||||
#[cfg(avr_mcu_atmega88pa)] pub use self::atmega88pa as current;
|
||||
|
||||
/// The ATmega328.
|
||||
///
|
||||
/// This device is chosen as the default when the crate is targeting non-AVR devices.
|
||||
#[cfg(any(avr_mcu_atmega328, feature = "all-mcus", not(target_arch = "avr")))] pub mod atmega328;
|
||||
#[cfg(any(avr_mcu_atmega328, not(target_arch = "avr")))] pub use self::atmega328 as current;
|
||||
|
||||
/// The ATmega168P.
|
||||
#[cfg(any(avr_mcu_atmega168p, feature = "all-mcus"))] pub mod atmega168p;
|
||||
#[cfg(avr_mcu_atmega168p)] pub use self::atmega168p as current;
|
||||
|
||||
/// The ATmega88P.
|
||||
#[cfg(any(avr_mcu_atmega88p, feature = "all-mcus"))] pub mod atmega88p;
|
||||
#[cfg(avr_mcu_atmega88p)] pub use self::atmega88p as current;
|
||||
|
||||
/// The ATmega168PA.
|
||||
#[cfg(any(avr_mcu_atmega168pa, feature = "all-mcus"))] pub mod atmega168pa;
|
||||
|
@ -44,18 +54,16 @@
|
|||
#[cfg(any(avr_mcu_atmega48p, feature = "all-mcus"))] pub mod atmega48p;
|
||||
#[cfg(avr_mcu_atmega48p)] pub use self::atmega48p as current;
|
||||
|
||||
/// The ATmega328.
|
||||
///
|
||||
/// This device is chosen as the default when the crate is targeting non-AVR devices.
|
||||
#[cfg(any(avr_mcu_atmega328, feature = "all-mcus", not(target_arch = "avr")))] pub mod atmega328;
|
||||
#[cfg(any(avr_mcu_atmega328, not(target_arch = "avr")))] pub use self::atmega328 as current;
|
||||
|
||||
/// The ATmega88A.
|
||||
#[cfg(any(avr_mcu_atmega88a, feature = "all-mcus"))] pub mod atmega88a;
|
||||
#[cfg(avr_mcu_atmega88a)] pub use self::atmega88a as current;
|
||||
|
||||
/// The ATmega48.
|
||||
#[cfg(any(avr_mcu_atmega48, feature = "all-mcus"))] pub mod atmega48;
|
||||
#[cfg(avr_mcu_atmega48)] pub use self::atmega48 as current;
|
||||
/// The ATmega32U4.
|
||||
#[cfg(any(avr_mcu_atmega32u4, feature = "all-mcus"))] pub mod atmega32u4;
|
||||
#[cfg(avr_mcu_atmega32u4)] pub use self::atmega32u4 as current;
|
||||
|
||||
/// The ATmega168.
|
||||
#[cfg(any(avr_mcu_atmega168, feature = "all-mcus"))] pub mod atmega168;
|
||||
#[cfg(avr_mcu_atmega168)] pub use self::atmega168 as current;
|
||||
|
||||
|
||||
|
|
|
@ -1,34 +1,38 @@
|
|||
mod clock;
|
||||
|
||||
|
||||
// FIXME: Start using this module or delete!!!
|
||||
#[allow(dead_code)] mod settings;
|
||||
#[allow(dead_code)]
|
||||
mod settings;
|
||||
|
||||
use crate::{Register, Pin};
|
||||
use crate::{Pin, Register};
|
||||
|
||||
/// An SPI module.
|
||||
///
|
||||
/// Information at [maxembedded.com](http://maxembedded.com/2013/11/the-spi-of-the-avr/).
|
||||
pub trait HardwareSpi {
|
||||
type MasterInSlaveOut: Pin;
|
||||
type MasterOutSlaveIn: Pin;
|
||||
type SerialDataIn: Pin;
|
||||
<<<<<<< Updated upstream
|
||||
type SerialDataOu: Pin;
|
||||
=======
|
||||
type SerialDataOut: Pin;
|
||||
>>>>>>> Stashed changes
|
||||
type Clock: Pin;
|
||||
type SlaveSelect: Pin;
|
||||
type ChipSelect: Pin;
|
||||
|
||||
/// The SPI control register.
|
||||
type ControlRegister: Register<T=u8>;
|
||||
type ControlRegister: Register<T = u8>;
|
||||
/// The SPI status register.
|
||||
type StatusRegister: Register<T=u8>;
|
||||
type StatusRegister: Register<T = u8>;
|
||||
/// The SPI data register.
|
||||
type DataRegister: Register<T=u8>;
|
||||
type DataRegister: Register<T = u8>;
|
||||
|
||||
/// Sets up the SPI as a master.
|
||||
fn setup_master(clock: u32) {
|
||||
// Setup DDR registers.
|
||||
Self::MasterInSlaveOut::set_input();
|
||||
Self::MasterOutSlaveIn::set_output();
|
||||
Self::SerialDataIn::set_input();
|
||||
Self::SerialDataOut::set_output();
|
||||
Self::Clock::set_output();
|
||||
Self::SlaveSelect::set_input();
|
||||
Self::ChipSelect::set_input();
|
||||
|
||||
Self::set_master();
|
||||
Self::enable_interrupt();
|
||||
|
@ -38,10 +42,10 @@ pub trait HardwareSpi {
|
|||
/// Sets up the SPI as a slave.
|
||||
fn setup_slave(clock: u32) {
|
||||
// Setup DDR registers.
|
||||
Self::MasterInSlaveOut::set_output();
|
||||
Self::MasterOutSlaveIn::set_input();
|
||||
Self::SerialDataIn::set_output();
|
||||
Self::SerialDataOut::set_input();
|
||||
Self::Clock::set_input();
|
||||
Self::SlaveSelect::set_input();
|
||||
Self::ChipSelect::set_input();
|
||||
|
||||
Self::set_slave();
|
||||
Self::setup_common(clock)
|
||||
|
@ -147,4 +151,3 @@ pub trait HardwareSpi {
|
|||
Self::DataRegister::read()
|
||||
}
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue